Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2013, Pages 203-209

  Ceyhan, Ahmet ^a   Naeemi, Azad ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Carbon nanotube FETs; Cu low k limitations; emerging carbon based interconnects; FinFETs; performance benchmarking; sub threshold CMOS; tunneling FETs

Indexed keywords

CARBON NANOTUBE FET; CARBON-BASED; CU/LOW-K; FINFETS; PERFORMANCE BENCHMARKING; SUBTHRESHOLD; TUNNELING FET;

BENCHMARKING; CARBON NANOTUBES; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUITS; NANORIBBONS; NANOWIRES;

TECHNOLOGY;

EID: 84879594704     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2013.6523611     Document Type: Conference Paper

References (30)

1. J. D. Meindl, A. Naeemi, M. Bakir, and R. Murali, "Nanoelectronics in retrospect, prospect, and principle," IEEE ISSCC, San Francisco, USA, Feb. 2010, pp. 31-35.
2. M. T. Bohr, "Interconnect scaling-the real limiter to high performance ULSI," International Electron Devices Meeting, Washington, DC, USA, Dec. 1995, pp. 241-244.
3. J. Deng, and H.-S. P. Wong, "A compact SPICE model for carbon nanotube field effect transistors including non-idealities and its application-part I: Model of the intrinsic channel region," IEEE Trans. Elec. Dev., vol. 54, no.12, pp. 3186-3194, Dec. 2007.
4. J. Deng, and and H.-S. P. Wong, "A compact SPICE model for carbon nanotube field effect transistors including non-idealities and its application-part II: Full device model and circuit performance benchmarking," IEEE Trans. Electron Devices, vol. 54, no.12, pp. 3195-3205, Dec. 2007.
5. B. Yu et al., "FinFET scaling to 10 nm gate length," International Electron Devices Meeting, Dec. 2002, pp. 251-254.
6. J. Appenzeller, J. Knoch, M. T. Bjork, H. Riel, H. Schmidt, and W. Reiss, "Toward nanowire electronics," IEEE Trans. Elec. Dev., vol. 55, no.11, Nov. 2008.
7. A. C. Seabaugh, and Q. Zhang, "Low-voltage tunnel transistors for beyond CMOS logic," Proceedings of the IEEE, vol. 98, no.12, Dec 2010.
8. A. Naeemi, and J. D. Meindl, "Carbon nanotube interconnects," Annu. Rev. Mater. Res., 2009, pp. 255-275.
9. A. Naeemi, and J. D. Meindl, "Compact physics-based circuit models for graphene nanoribbon interconnects," IEEE Trans. Electron Devices, vol. 56, no. 9, pp. 1822-1833, Sep. 2009.
10. V. Kumar, S. Rakheja, and A. Naeemi, "Performance and energy-per-bit modeling of multilayer graphene nanoribbon conductors," IEEE Trans. Electron Devices, vol. 59, no. 10, pp. 2753-2761, Oct. 2012.
11. G. Lopez, "The impact of interconnect process variations and size effects for gigascale integration," Ph.D. dissertation, Dept. Elec. Comp. Eng., Georgia Inst. Technol., Atlanta, GA, 2009.
12. W. Steinhoegl, G. Schindler, G. Steinlesberger, M. Traving, and M. Engelhardt, "Comprehensive study of the resistivity of copper wires with lateral dimensions of 100nm and smaller," J. Appl. Phys., vol. 97, 023706-0237067, 2005.
13. J. A. Davis et al., "Interconnect limits on gigascale integration (GSI) in the 21st century," Proc. IEEE, vol. 89, no. 3, pp. 305-324, Mar. 2001.
14. RAPHAEL, Synopsys Inc., Mountain Valley, CA, 1996.
15. HSPICE, Mountain View, CA: Synopsys Corp. Version 2008.09.
16. S. Sinha, G. Yeric, V. Chandra, B. Cline, and Y. Cao, "Exploring sub-20 nm FinFET design with predictive technology models," Design Automation Conference, 2012, pp.283-288.
17. Predictive Technology Models, Nanoscale Integration and Modeling Group,Arizona State University. [Online]. Available: http://ptm.asu.edu/
18. S. M. Sze, Physics of Semiconductors Devices, 2nd ed., 1981.
19. M. Luisier, and G. Klimeck, "Atomistic full-band design study of InAs band-to-band tunneling fieldeffect transistors," IEEE Elec. Dev. Lett., vol. 30, no. 6, June 2009.
20. S. Xiong, T.-J. King, and J. Bokor, "Study of the extrinsic parasitics in nano-scale transistors," Semicond. Sci. Technol., vol. 20, no. 6, pp. 652-657, May 2005.
21. C. T. White and T. N. Todorov, "Carbon nanotubes as long ballistic conductors," Nature, vol. 393, May 1998.
22. J. Park et al., "Electron-phonon scattering in metallic single-walled carbon nanotubes," Nano Lett., vol. 4, no. 3, pp. 517-520, 2004.
23. K. I. Bolotin et al., "Ultrahigh electron mobility in suspended graphene," Solid State Communications, 146, pp. 351-355, 2008.
24. U. E. Avci, R. Rios, K. J. Kung, I. A. Young, "Comparison of power and performance for the TFET and MOSFET and considerations for p-TFET," 11th IEEE Conf. on Nanotechnology, pp. 869-872, Aug. 2011.
25. A. Ceyhan and A. Naeemi, "Multi-level interconnect networks for the end of the roadmap: Conventional Cu/low-k and emerging carbon based interconnects," IEEE IITC, May 2011, pp. 1-3.
26. (2010). International Technology Roadmap for Semiconductors (ITRS), [Online]. Available: http://www.itrs.net/
27. N. Patil, J. Deng, S. Mitra, H.-S. P. Wong, "Circuitlevel performance benchmarking and scalability analysis of carbon nanotube transistor circuits," IEEE Trans. Nanotechnology, vol. 8, no. 1, Jan. 2009.
28. X. Wang, Y. Ouyang, X. Li, H. Wang, J. Guo, and H. Dai, "Room-temperature all-semiconducting sub-10 nm graphene nanoribbon field-effect transistors," Phys. Rev. Lett., vol. 100, no. 20, pp. 206803-1-206803-4, May 2008.
29. M. S. Dresselhaus, G. Dresselhaus, and P. Avouris, Eds., Topics in Applied Physics, Carbon Nanotubes: Synthesis, Structure, Properties and Applications, New York: Springer-Verlag, 2000.
30. A. A. Maarouf, C. L. Kane, and E. J. Mele, "Electronic structure of carbon nanotube ropes," Phy. Rev. B., vol. 61, no. 16, pp. 11156-11165, April 2000.