Comparison of power and performance for the TFET and MOSFET and considerations for P-TFET

Proceedings of the IEEE Conference on Nanotechnology

Volumn , Issue , 2011, Pages 869-872

  Avci, Uygar E ^a   Rios, Rafael ^a   Kuhn, Kelin J ^a   Young, Ian A ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DENSITY OF STATE; DEVICE CHARACTERISTICS; DEVICE DESIGN; GATE-LENGTH; INAS; LOGIC APPLICATIONS; MOS-FET; MOSFET TRANSISTORS; SI MOSFET; SOURCE DOPING; STANDBY POWER; SUPPLY VOLTAGES; SWITCHING ENERGY; TUNNELING FIELD-EFFECT TRANSISTORS; ULTRA LOW POWER;

CIRCUIT SIMULATION; INDIUM ARSENIDE; NANOTECHNOLOGY;

MOSFET DEVICES;

EID: 84858963634     PISSN: 19449399     EISSN: 19449380     Source Type: Conference Proceeding    
DOI: 10.1109/NANO.2011.6144631     Document Type: Conference Paper

References (6)

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3. U. E. Avci, R. Rios, K. Kuhn, I. A. Young, "Comparison of performance, switching energy and process variations for the TFET and MOSFET in logic," VLSI Technology (VLSIT), 2011 Symposium on, pp.124-125, 2011.
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