Highly energy-efficient SRAM with hierarchical bit line charge-sharing method using non-selected bit line charges

IEEE Journal of Solid-State Circuits

Volumn 48, Issue 4, 2013, Pages 924-931

  Miyano, Shinji ^a   Moriwaki, Shinichi ^a   Yamamoto, Yasue ^a   Kawasumi, Atsushi ^b   Suzuki, Toshikazu ^c   Sakurai, Takayasu ^d   Shinohara, Hirofumi ^a  

^a SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

^b TOSHIBA CORPORATION   (Japan)

^c PANASONIC CORPORATION   (Japan)

^d INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

Charge share; low power; low voltage; SRAM

Indexed keywords

65-NM TECHNOLOGIES; CHARGE SHARE; DYNAMIC POWER CONSUMPTION; ENERGY EFFICIENT; HIERARCHICAL BIT LINE; LOW POWER; LOW VOLTAGES; LOW-VOLTAGE SRAM;

ENERGY UTILIZATION; NANOTECHNOLOGY; STATIC RANDOM ACCESS STORAGE;

ENERGY EFFICIENCY;

EID: 84875717574     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2012.2237572     Document Type: Article

References (15)

1. S. R. Sridhara, M. Direnzo, S. Lingam, S. Lee, R. Blazquez, J. Maxey, S. Ghanem, Y. Lee, R. Abdallah, P. Singh, and M. Goel, "Microwatt embedded processor platform for medical system-on-chip applications," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2010, pp. 15-16.
2. S. Hsu, A. Agarwal, M. Anders, S. Mathew, H. Kaul, F. Sheikh, and R. Krishnamurthy, "A 280 mV-to-1.1 V 256 b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22 nm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2012, pp. 178-179.
3. S. Moriwaki,A.Kawasumi, T. Suzuki, T. Sakurai, and S.Miyano, "0.4 V SRAM with bit line swing suppression charge share hierarchical bit line scheme," in IEEE Custom Integrated Circuits Conf. Dig. Tech. Papers, Sep. 2011,M-6.
4. A. Kawasumi, T. Suzuki, S. Moriwaki, and S. Miyano, "Energy efficiency degradation caused by random variation in low-voltage SRAM and 26 energy reduction by Bitline Amplitude Limiting (BAL) scheme," in IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, Nov. 2012, pp. 165-168.
5. S. Moriwaki, Y. Yamamoto, A. Kawasumi, T. Suzuki, S. Miyano, T. Sakurai, andH. Shinohara, "A 13.8 pJ/Access/MbitSRAM with charge collector circuits for effective use of non-selected bit line charges," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2012, pp. 60-61.
6. M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Ohbayashi, Y. Nakase, and H. Shinohara, "A 45 nm 0.6 V cross-point 8T SRAM with negative biased read/write assist," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2009, pp. 158-159.
7. V. Ramadurai, H. Pilo, J. Andersen, G. Braceras, J. Gabric, D. Geise, S. Lamphier, and Y. Tan, "An 8 Mb SRAM in 45 nm SOI featuring a two-stage sensing scheme and dynamic power management," IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 155-162, Jan. 2009.
8. K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, Y. Oda, K. Usui, T. Kawamura, N. Tsuboi, T. Iwasaki, K. Hashimoto, H. Makino, and H. Shinohara, "A 45 nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2008, pp. 212-213.
9. V. Sharma, S. Cosemans, M. Ashouei, J. Huisken, F. Catthoor, and W. Dehaene, "A 4.4 pJ/Access 80 MHz, 2 K Word 64 b memory with write masking feature and variability resilient multi-sized sense amplifier redundancy for wireless sensor nodes applications," in Proc. Eur. Solid-State Circuits Conf., Sep. 2010, pp. 358-361.
10. S. Barasinski, L. Camus, and S. Clerc, "A 45 nm single power supply SRAM supporting low voltage operation down to 0.6 V," in Proc. Eur. Solid-State Circuits Conf., Sep. 2008, pp. 502-505.
11. K. Takeda, T. Saito, S. Asayama, Y. Aimoto, H. Kobatake, S. Ito, T. Takahashi, M. Nomura, K. Takeuchi, and Y. Hayashi, "Multi-step word-line control technology in hierarchical cell architecture for scaled-down high-density SRAMs," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2010, pp. 101-102.
12. M. Khellah, N. S. Kim, J. Howard, G. Ruhl, M. Sunna, Y. Ye, J. Tschanz, D. Somasekhar, N. Borkar, F. Hamzaoglu, G. Pandya, A. Farhang, K. Zhang, and V. De, "A4.2 GHz 0.3 mm 256 kb Dual-Vcc SRAM building block in 65 nm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2006, pp. 2752-2581.
13. B. Yang and L. Kim, "A low-power SRAM using hierarchical bit line and local sense amplifiers," IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1366-1376, Jun. 2005. (Pubitemid 40819379)
14. K. Kim, H. Mahmoodi, and K. Roy, "A low-power SRAM using bitline charge-recycling," IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 446-459, Feb. 2008.
15. Y. Yamamoto, A. Kawasumi, S. Moriwaki, T. Suzuki, S. Miyano, and H. Shinohara, "60 cycle time acceleration, 55% energy reduction 32 Kbit SRAM by Auto-Selective Boost (ASB) scheme for slow memory cells in random variations," in Proc. Eur. Solid-State Circuits Conf., Sep. 2012, pp. 317-320.