Multi-step word-line control technology in hierarchical cell architecture for scaled-down high-density SRAMs

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2010, Pages 101-102

  Takeda, K ^a   Saito, T ^a   Asayama, S ^a   Aimoto, Y ^a   Kobatake, H ^a   Ito, S ^a   Takahashi, T ^a   Takeuchi, K ^a   Nomura, M ^a   Hayashi, Y ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CELL ARCHITECTURES; CONTROL TECHNOLOGIES; HIGH-DENSITY; MULTI-STEP; POWER SUPPLY; RANDOM VARIABILITY;

STATIC RANDOM ACCESS STORAGE;

VLSI CIRCUITS;

EID: 77958002030     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2010.5560336     Document Type: Conference Paper

References (6)

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4. K. Zhang, et al., ISSCC 2005, pp. 474-475.
5. Y. Wang, et al., ISSCC 2009, pp. 456-457.
6. F. Arnaud, et al., IEDM 2009, pp. 651-654.