0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2011, Pages

  Moriwaki, Shinichi ^a   Kawasumi, Atsushi ^a   Suzuki, Toshikazu ^a   Sakurai, Takayasu ^b   Miyano, Shinji ^a  

^a SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIT LINES; CHARGE SHARING; FOUNDRY TECHNOLOGY; HIERARCHICAL BIT LINE; LOW VOLTAGE OPERATION; SWING SUPPRESSION;

INTEGRATED CIRCUITS;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 80455168120     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2011.6055398     Document Type: Conference Paper

References (8)

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