Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme

2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011

Volumn , Issue , 2011, Pages 165-168

  Kawasumi, Atsushi ^a   Suzuki, Toshikazu ^a   Moriwaki, Shinich ^a   Miyano, Shinji ^a  

^a SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AREA PENALTY; BIT LINES; CMOS TECHNOLOGY; DYNAMIC ENERGY; EFFICIENCY DEGRADATION; ENERGY DEGRADATION; ENERGY INCREASE; ENERGY REDUCTION; LOW-VOLTAGE; RANDOM VARIABILITY; RANDOM VARIATION; TOTAL ENERGY;

CMOS INTEGRATED CIRCUITS; DEGRADATION; ENERGY DISSIPATION; LIMITERS;

ENERGY EFFICIENCY;

EID: 84863069201     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2011.6123628     Document Type: Conference Paper

References (8)

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