An 8 Mb SRAM in 45 nm SOI featuring a two-stage sensing scheme and dynamic power management

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 1, 2009, Pages 155-162

  Ramadurai, Vinod ^a   Pilo, Harold ^a   Andersen, John ^a   Braceras, Geordie ^a   Gabric, John ^a   Geise, Daniel ^a   Lamphier, Steven ^a   Tan, Yue ^a  

^a IBM   (United States)

Author keywords

Low power; Memory; Power gating; SOI; SRAM

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; ELECTRIC POWER MEASUREMENT; ELECTRIC POWER UTILIZATION; ENERGY MANAGEMENT; SILICON ON INSULATOR TECHNOLOGY;

LOW POWER; MEMORY; POWER GATING; SOI; SRAM;

STATIC RANDOM ACCESS STORAGE;

EID: 58149236853     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2006433     Document Type: Conference Paper

References (8)

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