60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations

European Solid-State Circuits Conference

Volumn , Issue , 2012, Pages 317-320

  Yamamoto, Yasue ^a   Kawasumi, Atsushi ^b   Moriwaki, Shinichi ^a   Suzuki, Toshikazu ^c   Miyano, Shinji ^a   Shinohara, Hirofumi ^a  

^a SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

^b TOSHIBA CORPORATION   (Japan)

^c Panasonic   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; CYCLE TIME; ENERGY REDUCTION; LEAKAGE ENERGIES; MEMORY CELL; RANDOM VARIATION; SRAM MEMORY CELLS;

CMOS INTEGRATED CIRCUITS; LIMITERS;

ENERGY DISSIPATION;

EID: 84870805060     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2012.6341318     Document Type: Conference Paper

References (9)

1. S. Moriwaki, A. Kawasumi, T. Suzuki, T. Sakurai and S. Miyano, "0.4V SRAM with Bit Line Swing Suppression Charge Share Hierarchical Bit Line Scheme", IEEE CICC, pp.1-4, September 2011.
2. K. Takeda, T. Saito, S. Asayama, Y. Aimoto, H. Kobatake, S. Ito, T. Takahashi, K. Takeuchi, M. Nomura and Y. Hayashi, "Multi-step Word-line Control Technology in Hierarchical Cell Architecture for Scaled-down High-density SRAMs", IEEE Symposium on VLSI Circuits, pp.101-102, June 2010.
3. K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, Y. Oda, K. Usui, T. Kawamura, N. Tsuboi, T. Iwasaki, K. Hashimoto, H. Makino and H. Shinohara, "A 45-nm Single-port and Dual-port SRAM family with Robust Read/Write Stabilizing Circuitry under DVFS Environment", IEEE Symposium on VLSI Circuits, pp.212-213, June 2008.
4. M. Khellah, N.S. Kim, J. Howard, G. Ruhl, M. Sunna, Y. Ye, J. Tschanz, D. Somasekhar, N. Borkar, Fatih Hamzaoglu, G. Pandya, A. Farhang, K. Zhang and V. De, "A 4.2GHz 0.3mm2 256Kb Dual-Vcc SRAM Building Block in 65nm CMOS", IEEE ISSCC, Digest of Technical Papers, pp.2572-2581, February 2006.
5. S. Barasinski and L. Camus, "A 45nm single power supply SRAM supporting low voltage operation down to 0.6V", Proc. of European Solid-State Circuits Conference (ESSCIRC), pp.502-505, Sep 2008.
6. S. Cosemans, W. Dehaene and F. Catthoor, "A 3.6pJ/Access 480MHz, 128Kbit on-Chip SRAM with 850MHz Boost Mode in 90nm CMOS with Tunable Sense Amplifiers to Cope with Variability", Proc. of European Solid-State Circuits Conference (ESSCIRC), pp.278-281, Sep 2008.
7. V. Sharma, S. Cosemans, M. Ashouei, J. Huisken, F. Catthoor and W. Dehaene, "A 4.4pJ/Access 80MHz, 2K Word x 64b Memory with Write Masking Feature and Variability Resilient Multi-Sized Sense Amplifier Redundancy for Wireless Sensor Nodes Applications", Proc. of European Solid-State Circuits Conference (ESSCIRC), pp.358-361, Sep 2010.
8. A. Kawasumi, T. Suzuki, S. Moriwaki and S. Miyano, "Energy Efficiency Degradation Caused by Random Variation in Low-Voltage SRAM and 26% Energy Reduction by Bitline Amplitude Limiting (BAL) Scheme", IEEE ASSCC, pp.165-168, November 2011.
9. M. Khellah, N.S. Kim, Y. Ye, D. Somasekhar, T. Karnik, N. Borkar, F. Hamzaoglu, T. Coan, Y. Wang, K. Zhang, C. Webb and V. De, "PVT-Variations and Supply-Noise Tolerant 45nm Dense Cache Arrays with Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits", IEEE Symposium on VLSI Circuits, pp.48-49, June 2008.