A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2012, Pages 60-61

  Moriwaki, S ^a   Yamamoto, Y ^a   Kawasumi, A ^a   Suzuki, T ^b   Miyano, S ^a   Sakurai, T ^c   Shinohara, H ^a  

^a SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

^b PANASONIC CORPORATION   (Japan)

^c UNIVERSITY OF TOKYO   (Japan)

Author keywords

6T; charge share; SRAM

Indexed keywords

6T; BIT LINES; CHARGE COLLECTORS; CHARGE-SHARE; LOW VOLTAGES; POWER SOURCES; RANDOM VARIATION;

STATIC RANDOM ACCESS STORAGE;

VLSI CIRCUITS;

EID: 84866607086     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2012.6243789     Document Type: Conference Paper

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