Exploration and optimization of 3-D integrated DRAM subsystems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 32, Issue 4, 2013, Pages 597-610

  Weis, Christian ^a   Loi, Igor ^b   Benini, Luca ^b   Wehn, Norbert ^a  

^a University of Koblenz Landau   (Germany)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

3 D integration; channel; controller; DRAM

Indexed keywords

3-D INTEGRATION; ARCHITECTURE DESIGNS; CHANNEL; CONTROLLER ARCHITECTURES; OPTIMIZATION CRITERIA; POWER ESTIMATIONS; THROUGH-SILICON VIA (TSV) TECHNOLOGIES; TRADITIONAL APPROACHES;

CONTROLLERS; ENERGY EFFICIENCY; ENERGY UTILIZATION; MOBILE DEVICES; OPTIMIZATION; THREE DIMENSIONAL;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84875163754     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2012.2235125     Document Type: Article

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