3D DRAM design and application to 3D multicore systems

IEEE Design and Test of Computers

Volumn 26, Issue 5, 2009, Pages 36-47

  Sun, Hongbin ^a   Zheng, Nanning ^a   Liu, Jibang ^b   Anigundi, Rakesh S ^c   Lu, Jian Qiang ^b   Rose, Kenneth ^b   Zhang, Tong ^b  

^a XI'AN JIAOTONG UNIVERSITY   (China)

^b RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^c QUALCOMM INC   (United States)

Author keywords

3D integration; Computer architecture; Design and test; DRAM; Energy consumption; Memory hierarchy; Multicore; Packaging; Random access memory; Routing; Solid modeling; Three dimensional displays

Indexed keywords

3D INTEGRATION; DRAM; ENERGY CONSUMPTION; MEMORY HIERARCHY; MULTICORE; RANDOM ACCESS MEMORY; ROUTING; SOLID MODELING; THREE DIMENSIONAL DISPLAYS;

CACHE MEMORY; COMPUTERS; DESIGN; DYNAMIC RANDOM ACCESS STORAGE; SOFTWARE ARCHITECTURE;

THREE DIMENSIONAL;

EID: 70350586564     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2009.105     Document Type: Article

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