CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2012, Pages 33-38

  Chen, Ke ^a,b   Li, Sheng ^b   Muralimanohar, Naveen ^b   Ahn, Jung Ho ^c   Brockman, Jay B ^a   Jouppi, Norman P ^b  

^a UNIVERSITY OF NOTRE DAME   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

^c Seoul National University   (South Korea)

Author keywords

3D architecture; DRAM; Main memory; Modeling; TSV

Indexed keywords

3-D INTEGRATION; 3D ARCHITECTURES; 3D STACKING; COARSE-GRAINED; DESIGN TRADEOFF; DRAM DESIGN; DRAM TECHNOLOGY; FULL SPECTRUM; IN-DEPTH STUDY; INTEGRATED POWER; MAIN MEMORY; MARGINAL BENEFIT; OFF-CHIP; OVER CURRENT; TIMING MODELING; TSV;

COMMERCE; DESIGN; DIES; DYNAMIC RANDOM ACCESS STORAGE; EXHIBITIONS; MEMORY ARCHITECTURE; MODELS;

THREE DIMENSIONAL;

EID: 84862084382     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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