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Volumn , Issue , 2011, Pages

DRAM-on-logic stack - Calibrated thermal and mechanical models integrated into PathFinding flow

Author keywords

3D; Characterization; Design flow

Indexed keywords

3D; 3D TECHNOLOGY; DESIGN AND TECHNOLOGY; DESIGN FLOW; DESIGN FLOWS; EXPERIMENTAL DATA; MEASUREMENT RESULTS; MECHANICAL CHARACTERIZATIONS; MECHANICAL MODEL; PATHFINDING; SUPPORT SYSTEMS;

EID: 80455168169     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2011.6055357     Document Type: Conference Paper
Times cited : (15)

References (8)
  • 1
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    • G. Van der Plas et al., "Design Issues and. Considerations for Low-Cost 3D TSV IC Technology,". ISSCC 2010
    • ISSCC 2010
    • Van Der Plas, G.1
  • 2
    • 79961208982 scopus 로고    scopus 로고
    • Stackable memory of 3D chip integration for mobile applications
    • S. Gu et al., "Stackable memory of 3D chip integration for mobile applications", IEDM 2008, pp 1-4
    • IEDM 2008 , pp. 1-4
    • Gu, S.1
  • 3
    • 78649879384 scopus 로고    scopus 로고
    • Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions
    • G. Van der Plas et al., "Verifying electrical/thermal/thermo- mechanical behavior of a 3D stack - Challenges and solutions", CICC 2010
    • CICC 2010
    • Van Der Plas, G.1
  • 4
    • 80455165445 scopus 로고    scopus 로고
    • 3D for Wireless Mobile Multimedia Applications - Opportunities and Challenges
    • G. Kimmich et al., "3D for Wireless Mobile Multimedia Applications - Opportunities and Challenges", ISSCC 2010
    • ISSCC 2010
    • Kimmich, G.1
  • 5
    • 79959315163 scopus 로고    scopus 로고
    • Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance
    • K. Mercha et al., "Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance", IEDM, 2010
    • (2010) IEDM
    • Mercha, K.1
  • 6
    • 78649886664 scopus 로고    scopus 로고
    • Simulation methodology and flow integration for 3D IC stress management
    • M. Nakamoto et al., "Simulation methodology and flow integration for 3D IC stress management", CICC 2010
    • CICC 2010
    • Nakamoto, M.1
  • 7
    • 77950958016 scopus 로고    scopus 로고
    • Compact thermal modeling of hot spots in advanced 3D-stacked ICs
    • C. Torregiani et al., "Compact thermal modeling of hot spots in advanced 3D-stacked ICs", EPTC 2009
    • EPTC 2009
    • Torregiani, C.1
  • 8
    • 51549099639 scopus 로고    scopus 로고
    • Holistic pathfinding: Virtual wireless chip design for advanced technology and design exploration
    • R. Radojcic et al., "Holistic pathfinding: virtual wireless chip design for advanced technology and design exploration", DAC 2008
    • DAC 2008
    • Radojcic, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.