Variation tolerant CLSAs for nanoscale Bulk-CMOS and FinFET SRAM

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn , Issue , 2012, Pages 471-474

  Tsai, Ming Fu ^a   Tsai, Jen Huan ^b   Fan, Ming Long ^a   Su, Pin ^a   Chuang, Ching Te ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Current Latch Based Sense Amplifier; FinFET; Offset; SRAM; Yield

Indexed keywords

ARRAY EFFICIENCY; BIT LINES; EXTENSIVE SIMULATIONS; FINFET; FINFET DEVICES; NANO SCALE; OFFSET; OFFSET ERRORS; SENSE AMPLIFIER; YIELD;

NANOTECHNOLOGY; RANDOM ERRORS; STATIC RANDOM ACCESS STORAGE;

INTEGRATED CIRCUITS;

EID: 84874179474     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCCAS.2012.6419074     Document Type: Conference Paper

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