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Volumn 2005, Issue , 2005, Pages 176-181

Leakage current based stabilization scheme for robust sense-amplifier design for yield enhancement in nano-scale SRAM

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; COMPUTER SYSTEM RECOVERY; LEAKAGE CURRENTS; NANOSTRUCTURED MATERIALS; STABILIZATION; STORAGE ALLOCATION (COMPUTER);

EID: 33846910535     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2005.73     Document Type: Conference Paper
Times cited : (5)

References (17)
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  • 2
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  • 3
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  • 4
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    • B. Wicht, et. al, "Yield and speed optimization of a latch type voltage sense amplifier", IEEE JSSC, vol. 39, July, 2004, pp. 1148-1158.
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  • 7
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    • Sarpeshkar, R.1    et., al.2
  • 8
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    • T. Kawahara, et. al. "A high-speed, small-area, threshold-voltage- mismatch compensation sense amplifier for gigabit-scale DRAM arrays," IEEE J SSC, vol. 28, July 1993, pp. 816 - 823.
    • (1993) IEEE J SSC , vol.28 , pp. 816-823
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  • 9
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.