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Volumn , Issue , 2009, Pages 263-267

A process variation tolerant self-compensating sense amplifier design

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE COMPENSATION; CD VARIATION; OXIDE THICKNESS; PARAMETRIC VARIATION; PROCESS VARIATION; SENSE AMPLIFIER; SIGNALING TECHNIQUES; STATISTICAL SIMULATION;

EID: 70349509049     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2009.50     Document Type: Conference Paper
Times cited : (10)

References (11)
  • 1
    • 70349534187 scopus 로고    scopus 로고
    • Circuit Design and the Micro-Architecture Challenges
    • Mike Leary and Marius Evers, "Circuit Design and the Micro-Architecture Challenges," AMD presentation to GSRC, 2004
    • (2004) AMD presentation to GSRC
    • Leary, M.1    Evers, M.2
  • 3
    • 26844435103 scopus 로고    scopus 로고
    • Sensing design issues in deep submicron CMOS SRAMs
    • May
    • A. Natrajan et al, "Sensing design issues in deep submicron CMOS SRAMs" in Proc. IEEE Int. May 2005.pp.42-45.
    • (2005) Proc. IEEE Int , pp. 42-45
    • Natrajan, A.1
  • 4
    • 0027576335 scopus 로고
    • A current controlled latch sense amplifier and a static power-saving input buffer for lowpower architecture
    • Apr
    • T. Kobayashi et al., "A current controlled latch sense amplifier and a static power-saving input buffer for lowpower architecture," IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 523-527, Apr. 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , Issue.4 , pp. 523-527
    • Kobayashi, T.1
  • 5
    • 33846910535 scopus 로고    scopus 로고
    • Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM
    • 18-21 Dec, Pages
    • S. Mukhopadhyay, et al "Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM" in Test Symposium, 2005. Proceedings. 14th Asian 18-21 Dec. 2005 Page(s):176 - 181
    • (2005) Test Symposium, 2005. Proceedings. 14th Asian , pp. 176-181
    • Mukhopadhyay, S.1
  • 6
    • 3042778488 scopus 로고    scopus 로고
    • Yield and speed optimization of a latch type voltage sense amplifier
    • Jul
    • B. Wicht et al., "Yield and speed optimization of a latch type voltage sense amplifier," IEEE J. Solid-State Circuits, vol. 39, no. 7, pp.1148-1158, Jul. 2004.
    • (2004) IEEE J. Solid-State Circuits , vol.39 , Issue.7 , pp. 1148-1158
    • Wicht, B.1
  • 7
    • 0026238170 scopus 로고
    • Mismatch sensitivity of a simultaneously latched CMOS sense amplifier
    • Oct
    • R. Sarpeshkar et. al, "Mismatch sensitivity of a simultaneously latched CMOS sense amplifier," IEEE JSSC, vol. 26, Oct. 1991 pp. 1413 - 1422.
    • (1991) IEEE JSSC , vol.26 , pp. 1413-1422
    • Sarpeshkar, R.1    et., al.2
  • 9
    • 33644998470 scopus 로고    scopus 로고
    • S.Mukhopadhyay, et al. A Novel High-Performance and Robust Sense Amplifier Using Independent Gate Control in Sub-50-nm Double-Gate MOSFET in Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 14, Issue 2, Feb. 2006 Page(s):183 - 192.
    • S.Mukhopadhyay, et al. "A Novel High-Performance and Robust Sense Amplifier Using Independent Gate Control in Sub-50-nm Double-Gate MOSFET" in Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume 14, Issue 2, Feb. 2006 Page(s):183 - 192.
  • 10
    • 70349529352 scopus 로고    scopus 로고
    • http://www.eas.asu.edu/~ptm/
  • 11
    • 70349542303 scopus 로고    scopus 로고
    • http://www.research.ibm.com/DAMOCLES/


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.