-
1
-
-
51549113852
-
Comparison of multiple cell upset response of bulk and SOI 130 nm technologies in the terrestrial environment
-
May
-
G. Gasiot, P. Roche, and P. Flatresse, "Comparison of multiple cell upset response of bulk and SOI 130 nm technologies in the terrestrial environment," in Proc. IEEE Int. Reliability Phys. Symp., May 2008, pp. 192-194.
-
(2008)
Proc. IEEE Int. Reliability Phys. Symp
, pp. 192-194
-
-
Gasiot, G.1
Roche, P.2
Flatresse, P.3
-
2
-
-
83755163853
-
An area-efficient 65 nm radiation-hard dual-modular flip-flop to avoid multiple cell upsets
-
Dec.
-
R. Yamamoto, C. Hamanaka, J. Furuta, K. Kobayashi, and H. Onodera, "An area-efficient 65 nm radiation-hard dual-modular flip-flop to avoid multiple cell upsets," IEEE Trans. Nucl. Sci., vol. 58, no. 6, pp. 3053-3059, Dec. 2011.
-
(2011)
IEEE Trans. Nucl. Sci.
, vol.58
, Issue.6
, pp. 3053-3059
-
-
Yamamoto, R.1
Hamanaka, C.2
Furuta, J.3
Kobayashi, K.4
Onodera, H.5
-
3
-
-
80052778470
-
Investigation of multi cell upset in sequential logic and validity of redundancy technique
-
Jul.
-
T. Uemura, T. Kato, H. Matsuyama, K. Takahisa, M. Fukuda, and K. Hatanaka, "Investigation of multi cell upset in sequential logic and validity of redundancy technique," in Proc. IEEE Int. On-Line Testing Symp., Jul. 2011, pp. 7-12.
-
(2011)
Proc. IEEE Int. On-Line Testing Symp
, pp. 7-12
-
-
Uemura, T.1
Kato, T.2
Matsuyama, H.3
Takahisa, K.4
Fukuda, M.5
Hatanaka, K.6
-
4
-
-
79959309387
-
Neutron induced single event multiple transients with voltage scaling and body biasing
-
Apr.
-
R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Neutron induced single event multiple transients with voltage scaling and body biasing," in Proc. IEEE Int. Reliability Phys. Symp., Apr. 2011, pp. 3C.4.1-3C.4.5.
-
(2011)
Proc. IEEE Int. Reliability Phys. Symp.
-
-
Harada, R.1
Mitsuyama, Y.2
Hashimoto, M.3
Onoye, T.4
-
5
-
-
79959307359
-
Double-pulse-single-event transients in combinational logic
-
Apr.
-
J. R. Ahlbin, T. D. Loveless, D. R. Ball, B. L. Bhuva, A. F. Witulski, L.W. Massengill, and M. J. Gadlage, "Double-pulse-single-event transients in combinational logic," in Proc. IEEE Int. Reliability Phys. Symp., Apr. 2011, pp. 3C.5.1-3C.5.6.
-
(2011)
Proc. IEEE Int. Reliability Phys. Symp.
-
-
Ahlbin, J.R.1
Loveless, T.D.2
Ball, D.R.3
Bhuva, B.L.4
Witulski, A.F.5
Massengill, L.W.6
Gadlage, M.J.7
-
6
-
-
51549121623
-
A novel technique for mitigating neutron-induced multi-cell upset by means of back bias
-
May
-
T. Nakauchi, N. Mikami, A. Oyama, H. Kobayashi, H. Usui, and J. Kase, "A novel technique for mitigating neutron-induced multi-cell upset by means of back bias," in Proc. IEEE Int. Reliability Phys. Symp., May 2008, pp. 187-191.
-
(2008)
Proc. IEEE Int. Reliability Phys. Symp.
, pp. 187-191
-
-
Nakauchi, T.1
Mikami, N.2
Oyama, A.3
Kobayashi, H.4
Usui, H.5
Kase, J.6
-
7
-
-
58849091394
-
Characterizing SRAM single event upset in terms of single and multiple node charge collection
-
Dec.
-
J. D. Black, D. R. Ball, W. H. Robinson, D. M. Fleetwood, R. D. Schrimpf, R. A. Reed, D. A. Black, K. M. Warren, A. D. Tipton, P. E. Dodd, N. F. Haddad, M. A. Xapsos, H. S. Kim, and M. Friendlich, "Characterizing SRAM single event upset in terms of single and multiple node charge collection," IEEE Trans. Nucl. Sci., vol. 55, no. 6, pp. 2943-2947, Dec. 2008.
-
(2008)
IEEE Trans. Nucl. Sci.
, vol.55
, Issue.6
, pp. 2943-2947
-
-
Black, J.D.1
Ball, D.R.2
Robinson, W.H.3
Fleetwood, D.M.4
Schrimpf, R.D.5
Reed, R.A.6
Black, D.A.7
Warren, K.M.8
Tipton, A.D.9
Dodd, P.E.10
Haddad, N.F.11
Xapsos, M.A.12
Kim, H.S.13
Friendlich, M.14
-
8
-
-
83855165155
-
Impact of well structure on single-event well potential modulation in bulk CMOS
-
Dec.
-
N. J. Gaspard, A. F. Witulski, N. M. Atkinson, J. R. Ahlbin, W. T. Holman, B. L. Bhuva, T. D. Loveless, and L. W. Massengill, "Impact of well structure on single-event well potential modulation in bulk CMOS," IEEE Trans. Nucl. Sci., vol. 58, no. 6, pp. 2614-2620, Dec. 2011.
-
(2011)
IEEE Trans. Nucl. Sci.
, vol.58
, Issue.6
, pp. 2614-2620
-
-
Gaspard, N.J.1
Witulski, A.F.2
Atkinson, N.M.3
Ahlbin, J.R.4
Holman, W.T.5
Bhuva, B.L.6
Loveless, T.D.7
Massengill, L.W.8
-
9
-
-
33144454816
-
Investigation of multi-bit upsets in a 150 nm technology SRAM device
-
DOI 10.1109/TNS.2005.860675
-
D. Radaelli, H. Puchner, S. Wong, and S. Daniel, "Investigation of multi-bit upsets in a 150 nm technology SRAM device," IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2433-2437, Dec. 2005. (Pubitemid 43269622)
-
(2005)
IEEE Transactions on Nuclear Science
, vol.52
, Issue.6
, pp. 2433-2437
-
-
Radaelli, D.1
Puchner, H.2
Wong, S.3
Daniel, S.4
-
10
-
-
58849134896
-
Device-orientation effects on multiple-bit upset in 65 nm SRAMs
-
Dec.
-
A. D. Tipton, J. A. Pellish, J. M. Hutson, R. Baumann, X. Deng, A. Marshall, M. A. Xapsos, H. S. Kim, M. R. Friendlich, M. J. Campola, C. M. Seidleck, K. A. LaBel, M. H. Mendenhall, R. A. Reed, R. D. Schrimpf, R. A. Weller, and J. D. Black, "Device-orientation effects on multiple-bit upset in 65 nm SRAMs," IEEE Trans. Nucl. Sci., vol. 55, no. 6, pp. 2880-2885, Dec. 2008.
-
(2008)
IEEE Trans. Nucl. Sci.
, vol.55
, Issue.6
, pp. 2880-2885
-
-
Tipton, A.D.1
Pellish, J.A.2
Hutson, J.M.3
Baumann, R.4
Deng, X.5
Marshall, A.6
Xapsos, M.A.7
Kim, H.S.8
Friendlich, M.R.9
Campola, M.J.10
Seidleck, C.M.11
Label, K.A.12
Mendenhall, M.H.13
Reed, R.A.14
Schrimpf, R.D.15
Weller, R.A.16
Black, J.D.17
-
11
-
-
54949105433
-
Increased rate of multiple-bit upset from neutrons at large angles of incidence
-
Sep.
-
A. D. Tipton, X. Zhu, H. Weng, J. A. Pellish, P. R. Fleming, R. D. Schrimpf, R. A. Reed, R. A. Weller, and M. Mendenhall, "Increased rate of multiple-bit upset from neutrons at large angles of incidence," IEEE Trans. Device Mater. Rel., vol. 8, no. 3, pp. 565-570, Sep. 2008.
-
(2008)
IEEE Trans. Device Mater. Rel.
, vol.8
, Issue.3
, pp. 565-570
-
-
Tipton, A.D.1
Zhu, X.2
Weng, H.3
Pellish, J.A.4
Fleming, P.R.5
Schrimpf, R.D.6
Reed, R.A.7
Weller, R.A.8
Mendenhall, M.9
-
12
-
-
45849102786
-
Effects of guard bands and well contacts in mitigating long SETs in advanced CMOS processes
-
Jun.
-
B.Narasimham, B. L. Bhuva, R. D. Schrimpf, L.W.Massengill,M. J. Gadlage, T.W. Holman, A. F. Witulski, W. H. Robinson, J. D. Black, J. M. Benedetto, and P. H. Eaton, "Effects of guard bands and well contacts in mitigating long SETs in advanced CMOS processes," IEEE Trans. Nucl. Sci., vol. 55, no. 3, pp. 1708-1713, Jun. 2008.
-
(2008)
IEEE Trans. Nucl. Sci.
, vol.55
, Issue.3
, pp. 1708-1713
-
-
Narasimham, B.1
Bhuva, B.L.2
Schrimpf, R.D.3
Gadlage, L.J.4
Holman, T.W.5
Witulski, A.F.6
Robinson, W.H.7
Black, J.D.8
Benedetto, J.M.9
Eaton, P.H.10
-
13
-
-
84856363689
-
Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65 nm
-
Nov.
-
J. Furuta, R. Yamamoto, K. Kobayashi, and H. Onodera, "Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65 nm," in Proc. Asian Solid-State Circuit Conf., Nov. 2011, pp. 209-212.
-
(2011)
Proc. Asian Solid-State Circuit Conf
, pp. 209-212
-
-
Furuta, J.1
Yamamoto, R.2
Kobayashi, K.3
Onodera, H.4
-
14
-
-
84866599466
-
Evaluation of parasitic bipolar effects on neutron-induced SET rates for logic gates
-
Apr.
-
J. Furuta, R. Yamamoto, K. Kobayashi, and H. Onodera, "Evaluation of parasitic bipolar effects on neutron-induced SET rates for logic gates," in Proc. IEEE Int. Reliability Phys. Symp., Apr. 2012, pp. SE.5.1-SE.5.5.
-
(2012)
Proc. IEEE Int. Reliability Phys. Symp.
-
-
Furuta, J.1
Yamamoto, R.2
Kobayashi, K.3
Onodera, H.4
-
15
-
-
46449085015
-
Evaluating fault coverage of bulk built-in current sensor for soft errors in combinational and sequential logic
-
Sep.
-
E. H. Neto, I. Ribeiro, M. Vieira, G. Wirth, and F. L. Kastensmidt, "Evaluating fault coverage of bulk built-in current sensor for soft errors in combinational and sequential logic," in VLSI Cir. Symp., Sep. 2005, pp. 62-67.
-
(2005)
VLSI Cir. Symp.
, pp. 62-67
-
-
Neto, E.H.1
Ribeiro, I.2
Vieira, M.3
Wirth, G.4
Kastensmidt, F.L.5
-
16
-
-
39749200969
-
Case study of a low power MTCMOS based ARM926 SoC: Design, analysis and test challenges
-
Oct.
-
S. Idgunji, "Case study of a low power MTCMOS based ARM926 SoC: Design, analysis and test challenges," in IEEE Int. Test Conf., Oct. 2007, pp. 1-10.
-
(2007)
IEEE Int. Test Conf.
, pp. 1-10
-
-
Idgunji, S.1
|