Evaluation of parasitic bipolar effects on neutron-induced SET rates for logic gates

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2012, Pages

  Furuta, Jun ^a   Yamamoto, Ryosuke ^b   Kobayashi, Kazutoshi ^b   Onodera, Hidetoshi ^a,c  

^a KYOTO UNIVERSITY   (Japan)

^b KYOTO INSTITUTE OF TECHNOLOGY   (Japan)

^c JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR AMPLIFICATION; BIPOLAR EFFECTS; CLOCK BUFFER; CMOS PROCESSS; IN-LINE; MEASURED RESULTS; PULSEWIDTHS; SINGLE EVENT TRANSIENTS; TRIPLE WELL;

CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS;

TRANSIENTS;

EID: 84866599466     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2012.6241930     Document Type: Conference Paper

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