An area-efficient 65 nm radiation-hard dual-modular flip-flop to avoid multiple cell upsets

IEEE Transactions on Nuclear Science

Volumn 58, Issue 6 PART 1, 2011, Pages 3053-3059

  Yamamoto, Ryosuke ^a   Hamanaka, Chikara ^a   Furuta, Jun ^b   Kobayashi, Kazutoshi ^c   Onodera, Hidetoshi ^b,c  

^a KYOTO INSTITUTE OF TECHNOLOGY   (Japan)

^b KYOTO UNIVERSITY   (Japan)

^c JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

Author keywords

65 nm bulk CMOS; bi stable cross coupled dual modular (BCDMR); built in soft error resilience (BISER); dual interlocked storage cell (DICE); flip flop; multiple cell upset (MCU); radiation hard design

Indexed keywords

BISTABLES; BUILT-IN SOFT-ERROR RESILIENCE (BISER); BULK CMOS; DUAL-INTERLOCKED STORAGE CELL (DICE); FLIP-FLOP; MULTIPLE CELL UPSET;

CELLS; FLIP FLOP CIRCUITS;

NEUTRON IRRADIATION;

EID: 83755163853     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2011.2169457     Document Type: Conference Paper

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