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Volumn , Issue , 2011, Pages

Neutron induced single event multiple transients with voltage scaling and body biasing

Author keywords

[No Author keywords available]

Indexed keywords

BODY BIASING; BODY VOLTAGE; CMOS PROCESSS; MEASURED RESULTS; MEASUREMENT CIRCUIT; MEASUREMENT RESULTS; REVERSE BODY BIASING; SINGLE EVENT; SINGLE EVENT TRANSIENTS; SPATIAL SPREADING; TEST CHIPS; VOLTAGE-SCALING;

EID: 79959309387     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2011.5784485     Document Type: Conference Paper
Times cited : (55)

References (10)
  • 4
    • 28444432644 scopus 로고    scopus 로고
    • Multiple transient faults in logic: An issue for next generation ICs?
    • D. Rossi, M. Omana, F. Toma, and C. Metra, "Multiple transient faults in logic: An issue for next generation ICs?" in Proc. DFT, pp. 352-360, 2005.
    • (2005) Proc. DFT , pp. 352-360
    • Rossi, D.1    Omana, M.2    Toma, F.3    Metra, C.4
  • 6
    • 77957911501 scopus 로고    scopus 로고
    • LEAP: Layout Design through Error-Aware Transistor Positioning for soft-error resilient sequential cell design
    • H. Kelin, L. Klas, B. Mounaim, R. Prasanthi, I. Linscott, U. Inan, and S. Mitra, "LEAP: Layout Design through Error-Aware Transistor Positioning for soft-error resilient sequential cell design," in Proc. IRPS, pp. 203-212, 2010.
    • (2010) Proc. IRPS , pp. 203-212
    • Kelin, H.1    Klas, L.2    Mounaim, B.3    Prasanthi, R.4    Linscott, I.5    Inan, U.6    Mitra, S.7
  • 8
    • 77958012643 scopus 로고    scopus 로고
    • A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop capable of protecting soft errors on the C-element
    • J. Furuta, C. Hamanaka, K. Kobayashi, and H. Onodera, "A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop capable of protecting soft errors on the C-element," in Proc. VLSIC, pp. 123-124, 2010.
    • (2010) Proc. VLSIC , pp. 123-124
    • Furuta, J.1    Hamanaka, C.2    Kobayashi, K.3    Onodera, H.4
  • 9
    • 21644463896 scopus 로고    scopus 로고
    • Comprehensive study of soft errors in advanced CMOS circuits with 90/130 nm technology
    • Y. Tosaka, H. Ehara, M. Igeta, T. Uemura, H. Oka, N. Matsuoka, and K. Hatanaka, "Comprehensive study of soft errors in advanced CMOS circuits with 90/130 nm technology," in Proc. IEDM, pp. 941-944, 2005.
    • (2005) Proc. IEDM , pp. 941-944
    • Tosaka, Y.1    Ehara, H.2    Igeta, M.3    Uemura, T.4    Oka, H.5    Matsuoka, N.6    Hatanaka, K.7


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.