On logic synthesis for timing speculation

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2012, Pages 591-596

  Liu, Yuxi ^a   Ye, Rong ^a   Yuan, Feng ^a   Kumar, Rakesh ^b   Xu, Qiang ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); DELAY CIRCUITS; ENERGY EFFICIENCY; ERRORS; GATES (TRANSISTOR); LOGIC CIRCUITS; LOGIC SYNTHESIS; STRUCTURAL OPTIMIZATION; TIMING CIRCUITS;

BENCHMARK CIRCUIT; CIRCUIT STRUCTURES; CIRCUIT TIMING; DELAY DISTRIBUTIONS; LOGIC OPTIMIZATION; NANOMETER TECHNOLOGY; OPTIMIZATION TECHNIQUES; TIMING SPECULATIONS;

COMPUTER CIRCUITS;

EID: 84872343313     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2429384.2429512     Document Type: Conference Paper

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