메뉴 건너뛰기




Volumn , Issue , 2010, Pages 1554-1559

TIMBER: Time borrowing and error relaying for online timing error resilience

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; ECONOMIC AND SOCIAL EFFECTS; FLIP FLOP CIRCUITS; TIMBER; TIMING CIRCUITS;

EID: 77953099989     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2010.5457058     Document Type: Conference Paper
Times cited : (74)

References (20)
  • 2
    • 35348837202 scopus 로고    scopus 로고
    • ReCycle: Pipeline adaptation to tolerate process variation
    • A. Tiwari et al., "ReCycle: Pipeline adaptation to tolerate process variation," in Proc. Intl. Symposium on Computer Architecture, pp. 323-334, 2007.
    • (2007) Proc. Intl. Symposium on Computer Architecture , pp. 323-334
    • Tiwari, A.1
  • 3
    • 57849113951 scopus 로고    scopus 로고
    • Timing yield enhancement through soft edge flip-flop based design
    • M. Wieckowski et al., "Timing yield enhancement through soft edge flip-flop based design," in Proc. Custom Integrated Circuits Conference, pp. 543-546, 2008.
    • (2008) Proc. Custom Integrated Circuits Conference , pp. 543-546
    • Wieckowski, M.1
  • 4
    • 63149170541 scopus 로고    scopus 로고
    • Revival: A variation-tolerant architecture using voltage interpolation and variable latency
    • L. X. Liang et al., "Revival: A variation-tolerant architecture using voltage interpolation and variable latency," Proc. Intl. Symposium on Microarchitecture, vol. 29, pp. 127-138, 2009.
    • (2009) Proc. Intl. Symposium on Microarchitecture , vol.29 , pp. 127-138
    • Liang, L.X.1
  • 5
    • 0028757145 scopus 로고
    • On-line delay testing of digital circuits
    • P. Franco et al., "On-line delay testing of digital circuits," in Proc. VLSI Test Symposium, pp. 167-173, 1994.
    • (1994) Proc. VLSI Test Symposium , pp. 167-173
    • Franco, P.1
  • 6
    • 0030104425 scopus 로고    scopus 로고
    • Sensing circuit for on-line detection of delay faults
    • M. Favalli et al., "Sensing circuit for on-line detection of delay faults," IEEE Trans. VLSI Systems, vol. 4, pp. 130-133, 1996.
    • (1996) IEEE Trans. VLSI Systems , vol.4 , pp. 130-133
    • Favalli, M.1
  • 7
    • 0032317504 scopus 로고    scopus 로고
    • On-line detection of logic errors due to crosstalk, delay, and transient faults
    • C. Metra et al., "On-line detection of logic errors due to crosstalk, delay, and transient faults," in Proc. Intl. Test Conference, pp. 524-533, 1998.
    • (1998) Proc. Intl. Test Conference , pp. 524-533
    • Metra, C.1
  • 8
    • 0032684765 scopus 로고    scopus 로고
    • Time redundancy based soft error tolerance to rescue nanometer technologies
    • M. Nicolaidis, "Time redundancy based soft error tolerance to rescue nanometer technologies," in Proc. VLSI Test Symposium, pp. 86-94, 1999.
    • (1999) Proc. VLSI Test Symposium , pp. 86-94
    • Nicolaidis, M.1
  • 9
    • 84944071384 scopus 로고    scopus 로고
    • A sense amplifier based circuit for concurrent detection of soft and timing errors in CMOS ICs
    • Y. Tsiatouhas et al., "A sense amplifier based circuit for concurrent detection of soft and timing errors in CMOS ICs," in Proc. Intl. On-line Testing Symposium, pp. 12-16, 2003.
    • (2003) Proc. Intl. On-line Testing Symposium , pp. 12-16
    • Tsiatouhas, Y.1
  • 10
    • 37549010759 scopus 로고    scopus 로고
    • Circuit failure prediction and its application to transistor aging
    • M. Agarwal et al., "Circuit failure prediction and its application to transistor aging," in Proc. VLSI Test Symposium, pp. 277-286, 2007.
    • (2007) Proc. VLSI Test Symposium , pp. 277-286
    • Agarwal, M.1
  • 11
    • 34548124929 scopus 로고    scopus 로고
    • A simple flip-flop circuit for typical-case designs for DFM
    • T. Sato et al., "A simple flip-flop circuit for typical-case designs for DFM," in Proc. Intl. Symposium on Quality Electronic Design, pp. 539-544, 2007.
    • (2007) Proc. Intl. Symposium on Quality Electronic Design , pp. 539-544
    • Sato, T.1
  • 12
    • 70350712950 scopus 로고    scopus 로고
    • Circuit techniques for dynamic variation tolerance
    • K. Bowman et al., "Circuit techniques for dynamic variation tolerance," in Proc. Design Automation Conference, pp. 4-7, 2009.
    • (2009) Proc. Design Automation Conference , pp. 4-7
    • Bowman, K.1
  • 13
  • 14
    • 84944408150 scopus 로고    scopus 로고
    • Razor: A low-power pipeline based on circuit-level timing speculation
    • D. Ernst et al., "Razor: A low-power pipeline based on circuit-level timing speculation," in Proc. Intl. Symposium on Microarchitecture, pp. 7-18, 2003.
    • (2003) Proc. Intl. Symposium on Microarchitecture , pp. 7-18
    • Ernst, D.1
  • 15
    • 50849119316 scopus 로고    scopus 로고
    • Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance
    • K. Bowman et al., "Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance," in Proc. Intl. Conference on Integrated Circuit Design and Technology, pp. 155-158, 2008.
    • (2008) Proc. Intl. Conference on Integrated Circuit Design and Technology , pp. 155-158
    • Bowman, K.1
  • 16
    • 51549088217 scopus 로고    scopus 로고
    • Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling
    • M. Kurimoto et al., "Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling," in Proc. Design Automation Conference, pp. 884-889, 2008.
    • (2008) Proc. Design Automation Conference , pp. 884-889
    • Kurimoto, M.1
  • 17
    • 54249170090 scopus 로고    scopus 로고
    • Delay-compensation flip-flop with in-situ error monitoring for low-power and timing-error-tolerant circuit design
    • K. Hirose et al., "Delay-compensation flip-flop with in-situ error monitoring for low-power and timing-error-tolerant circuit design," Japanese Journal of Applied Physics, vol. 47, pp. 2779-2787, 2008.
    • (2008) Japanese Journal of Applied Physics , vol.47 , pp. 2779-2787
    • Hirose, K.1
  • 19
    • 23844466920 scopus 로고    scopus 로고
    • Impact of NBTI on the temporal performance degradation of digital circuits
    • B. Paul et al., "Impact of NBTI on the temporal performance degradation of digital circuits," IEEE Electron Device Letters, vol. 26, pp. 560-562, 2005.
    • (2005) IEEE Electron Device Letters , vol.26 , pp. 560-562
    • Paul, B.1
  • 20
    • 57549091018 scopus 로고    scopus 로고
    • A mathematical solution to power optimal pipeline design by utilizing soft-edge flip-flops
    • M. Ghasemazar et al., "A mathematical solution to power optimal pipeline design by utilizing soft-edge flip-flops," in Proc. Intl. Symposium on Low Power Electronics and Design, pp. 33-38, 2008.
    • (2008) Proc. Intl. Symposium on Low Power Electronics and Design , pp. 33-38
    • Ghasemazar, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.