A re-design technique for datapath modules in error tolerant applications

Proceedings of the Asian Test Symposium

Volumn , Issue , 2008, Pages 431-437

  Shin, Doochul ^a   Gupta, Sandeep K ^a  

^a University of Southern California ^*

Author keywords

[No Author keywords available]

Indexed keywords

ADDER ARCHITECTURES; CORRECTING CODES; DESIGN TECHNIQUES; ERROR TOLERANCES; MANUFACTURING DEFECTS; MANUFACTURING YIELDS; PARAMETRIC YIELDS; TEST TECHNIQUES; WIRELESS COMMUNICATIONS;

ADDERS; APPLICATIONS; ARTIFICIAL INTELLIGENCE; COSINE TRANSFORMS; ERRORS; INFORMATION THEORY;

YTTRIUM ALLOYS;

EID: 58249108410     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2008.75     Document Type: Conference Paper

References (22)

1. R.C. Leachman and C. N. Berglund, "Systematic Mechanisms Limited Yield (SMLY) Study", International SEMATECH, DOC #03034383A-ENG, 2003.
2. M. A. Breuer, "Intelligible Test Techniques to Support Error-Tolerance", Proc. 13th Asian Test Symposium, 2004.
3. M. A. Breuer, S. K. Gupta and T. M. Mak, "Defect and Error-Tolerance in the Presence of Massive Numbers of Defects", IEEE Design and Test Magazine, 2004.
4. I. Chong, H. Y. Cheong, and A. Ortega, "New Quality Metric for Multimedia Compression Using Faulty Hardware", Proc. International Workshop on Video Processing and Quality Metrics for Consumer Electronics, 2006.
5. H. Chung and A. Ortega, "Analysis and Testing for Error Tolerant Motion Estimation" Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI System, 2005.
6. I. Chong and A. Ortega, "Hardware Testing For Error Tolerant Multimedia Compression based on Linear Transforms", Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2005.
7. S. Shahidi and S. K. Gupta, "A theory of Error-Rate Testing", Proc. International Conference on Computer Design, 2006.
8. Z. Jiang and S. K. Gupta, "An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes", Proc. International Test Conference, 2002.
9. A. Srivastava, D. Sylvester and D. Blaauw, Statistical Analysis and Optimization for VLSI: Timing and Power, Springer, 2005.
10. V. Kantabutra, "Designing optimum carry-skip adders", Proc. IEEE Symposium on Computer Arithmetic, 1991.
11. R. M. Warner, "Applying a composite model to the IC yield problem," IEEE Journal of Solid-State Circuits, 1974.
12. I. Koren, Computer Arithmetic Algorithms, A. K. Peters, 2002.
13. W. Maly, "Cost of silicon viewed from VLSI design perspective," Proc. IEEE Design Automation Conference, 1994.
14. I. E. Sutherland, R. F. Sproull and D. L. Harris, Logical Effort, Designing Fast CMOS Circuits, Morgan Kaufmann, 1999.
15. N. Jha and S. K. Gupta. Testing of Digital Systems, Cambridge University Press, 2003.
16. M. Abramovici, M. A. Breuer and A. D. Friedman, Digital SystemsTesting and Testable Design, John Wiley and Sons, 1995.
17. M. Kovac, N. Ranganathan, "JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard", Proc International conference on VLSI design, 1995.
18. G. V. Varatkar, N. R. Shanbhag, " Variation-Tolerant Motion Estimation Architecture", Proc. IEEE workshop on Signal Processing Systems, 2007.
19. B. Gorjiara, M. Reshadi, D. Gajski, "Designing a custom architecture for DCT using NISC technology", Proc. Asia and South Pacific conference on Design Automation, 2006.
20. J. L. Hennessy, D. A. Patterson, Computer Architecture: A Quantitative Approach, Third Edition, Morgan Kaufmann, 2002.
21. J. Fritts, W. Wolf and B. Liu, "Understanding multimedia application characteristics for designing programmable media processors", Proc. SPIE,1999.
22. A. Shams, M. Bayoumi, "A 108 Gbps, 1.5 GHz 1D-DCT architecture", Proc. IEEE International Conference on Application-Specific Systems, Architectures, and Processors, 2000.