Variation-aware low-power synthesis methodology for fixed-point FIR filters

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 1, 2009, Pages 87-97

  Choi, Jung Hwan ^a   Banerjee, Nilanjan ^b   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Finite impulse response (FIR) filter synthesis; Low power methodology; Variation aware design

Indexed keywords

AVERAGE POWER; CRITICAL PATHS; DELAY VARIATION; FILTER COEFFICIENTS; FILTER QUALITY; FILTER RESPONSE; FINITE IMPULSE RESPONSE FILTER; GRACEFUL DEGRADATION; IMPORTANT COEFFICIENTS; LOW POWER; LOW-POWER DISSIPATION; LOW-POWER SYNTHESIS; PROCESS PARAMETER VARIATIONS; PROCESS VARIATION; PROPOSED ARCHITECTURES; SUPPLY-VOLTAGE SCALING; VARIATION-AWARE DESIGN; VOLTAGE-SCALING;

ADDERS; DEGRADATION; IMPULSE RESPONSE;

FIR FILTERS;

EID: 77955154464     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.2009135     Document Type: Article

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