메뉴 건너뛰기




Volumn 6313, Issue , 2006, Pages

Estimating adders for a low density parity check decoder

Author keywords

Computer arithmetic; Error control codes; Estimating arithmetic; IEEE 802.16e; LDPC

Indexed keywords

COMPUTATION THEORY; DECODING; DIGITAL ARITHMETIC; ERROR CORRECTION; LOGIC DESIGN;

EID: 33750584404     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.680199     Document Type: Conference Paper
Times cited : (23)

References (10)
  • 1
    • 33646512383 scopus 로고    scopus 로고
    • Arithmetic data value speculation
    • ACSAC 2005, T. Srikanthan, ed., Springer
    • D. Kelly and B. Phillips, "Arithmetic data value speculation," in ACSAC 2005, T. Srikanthan, ed., Lecture Notes in Computer Science 3740, pp. 353-366, Springer, 2005.
    • (2005) Lecture Notes in Computer Science , vol.3740 , pp. 353-366
    • Kelly, D.1    Phillips, B.2
  • 3
    • 1842425446 scopus 로고    scopus 로고
    • Speeding up processing with approximation circuits
    • S.-L. Lu, "Speeding up processing with approximation circuits," Computer 37(3), pp. 67-73, 2004.
    • (2004) Computer , vol.37 , Issue.3 , pp. 67-73
    • Lu, S.-L.1
  • 4
    • 84925405668 scopus 로고
    • Low density parity check codes
    • Jan.
    • R. Gallager, "Low density parity check codes," IRE Trans. Inform. Theory, IT-8, pp. 21-28, Jan. 1962.
    • (1962) IRE Trans. Inform. Theory , vol.IT-8 , pp. 21-28
    • Gallager, R.1
  • 5
    • 0035246127 scopus 로고    scopus 로고
    • Design of capacity-approaching irregular low-density parity-check codes
    • Feb.
    • T. J. Richardson, M. A. Shokrollahi, and R. L. Urbanke, "Design of capacity-approaching irregular low-density parity-check codes," IEEE Trans. Inform. Theory, 47, pp. 619-637, Feb. 2001.
    • (2001) IEEE Trans. Inform. Theory , vol.47 , pp. 619-637
    • Richardson, T.J.1    Shokrollahi, M.A.2    Urbanke, R.L.3
  • 9
    • 0036504121 scopus 로고    scopus 로고
    • A 690-mW 1-Gb/s 1024-b, Rate-1/2 low-density parity-check code decoder
    • Mar.
    • A. J. Blanksby and C. J. Rowland, "A 690-mW 1-Gb/s 1024-b, Rate-1/2 low-density parity-check code decoder," IEEE Journal of Solid-State Circuits 37, pp. 404-412, Mar. 2002.
    • (2002) IEEE Journal of Solid-state Circuits , vol.37 , pp. 404-412
    • Blanksby, A.J.1    Rowland, C.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.