Scaling energy per operation via an asynchronous pipeline

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 21, Issue 1, 2013, Pages 147-151

  Marr, Bo ^a   Degnan, Brian ^b   Hasler, Paul ^b   Anderson, David ^b  

^a RAYTHEON COMPANY   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Asynchronous circuits; digital integrated circuits; energy efficiency; integrated circuit modeling; performance analysis; power consumption

Indexed keywords

ASYNCHRONOUS CIRCUITS; ASYNCHRONOUS PIPELINE; ASYNCHRONOUS SYSTEM; DATA SETS; ENERGY EFFICIENT; ENERGY MODEL; FULLY PIPELINED; INTEGRATED CIRCUIT MODELING; PER UNIT; PERFORMANCE ANALYSIS; RATE-OF-ENERGY; SUBTHRESHOLD;

DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; ENERGY EFFICIENCY;

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 84871724333     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2011.2178126     Document Type: Article

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