An asynchronously embedded datapath for performance acceleration and energy efficiency

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2009, Pages 3046-3049

  Marr, Bo ^a   Degnan, Brian ^a   Hasler, Paul ^a   Anderson, David V ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARITHMETIC LOGIC; DATA PATH DESIGN; DATA PATHS; DATA-PATH UNITS; DATAPATH CIRCUITS; ENCODING SCHEMES; LOW OVERHEAD; MEMORY ELEMENT; PERFORMANCE ACCELERATION; REGISTER FILES; SIMULATION RESULT; SUPPLY-VOLTAGE SCALING; TEST CHIPS; TIMING CONSTRAINTS; TIMING ERRORS;

ENERGY EFFICIENCY; TIME MEASUREMENT; TIMING CIRCUITS;

LOGIC CIRCUITS;

EID: 70350159188     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2009.5118445     Document Type: Conference Paper

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