Circuit design for voltage scaling and SER immunity on a quad-core Itanium® processor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 93-94

  Krueger, Dan ^a   Francom, Erin ^a   Langsdorf, Jack ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC FREQUENCY SCALING; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT MANUFACTURE; TIMING CIRCUITS; VOLTAGE SCALING;

CIRCUIT DESIGNS; ERROR RATE; ITANIUM; LOGIC CIRCUITRY; LOWER VOLTAGES; REGISTER FILES; UNPROTECTED STRUCTURES; VOLTAGE FREQUENCY;

COMPUTER CIRCUITS;

EID: 49549096949     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523073     Document Type: Conference Paper

References (4)

1. B. Stackhouse et al., "A 65nm 2-Billion Transistor Quad-Core Intel⊙ Itanium⊙ Processor", ISSCC Dig. Tech. Papers, pp. 92-93, Feb. 2008.
2. S. Naffziger, et al., "The Implementation of a 2-core, Multi-threaded Itanium⊙ Family Microprocessor", IEEE J. of Solid State Circuits, vol. 41, no. 1, pp. 197-209, 2006.
3. S. Naffziger et al, "The Implementation of the Itanium 2 Microprocessor", IEEE J. of Solid State Circuits, Vol. 37, No. 11 pp 1448-1460, 2002.
4. P. Hazucha, et al., "Measurements and Analysis of SER-Tolerant Latch in a 90-nm Dual-Vt Process", IEEE J. of Solid State Circuits, vol. 39, no. 9, pp. 1536-1543, 2004.