Nonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs for power-gating systems

Electronics Letters

Volumn 47, Issue 18, 2011, Pages 1027-1029

  Yamamoto, S ^a   Shuto, Y ^a   Sugahara, S ^a  

^a Tokyo Institute of Technology ^*  (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS LOGIC; ENERGY PERFORMANCE; MAGNETIC TUNNEL JUNCTION; NON-VOLATILE; POWER-GATING; SPIN TRANSFER TORQUE;

FLIP FLOP CIRCUITS; GATING AND FEEDING; LOGIC CIRCUITS; TUNNEL JUNCTIONS;

MAGNETIC DEVICES;

EID: 80053080783     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el.2011.1807     Document Type: Article

References (6)

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3. Hu, Z., Buyuktosunoglu, A., Srinivasan, V., Zyuban, V., Jacobson, H., and Bose, P.: ' Microarchitectural techniques for power gating of execution units ', Proc. 2004 ACM/IEEE Int. Symp. Low Power Electronics Design, Newport Beach, CA, USA, August, 2004, p. 32-37 (Pubitemid 40454678)
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