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Volumn 112, Issue 7, 2012, Pages

Investigation of vertically trapped charge locations in Cr-doped-SrTiO 3-based charge trapping memory devices

Author keywords

[No Author keywords available]

Indexed keywords

BOTTOM LAYERS; CHARGE TRAPPING MEMORIES; HIGH ELECTRIC FIELDS; HOLE INJECTION; HOLE TUNNELING; INTERFACE TRAP DENSITY; INTERFACE TRAPS; SI SUBSTRATES; TRAP SITES; TRAPPED CHARGE; TRAPPING EFFICIENCIES;

EID: 84867504513     PISSN: 00218979     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.4757413     Document Type: Article
Times cited : (1)

References (19)
  • 2
    • 77749323318 scopus 로고    scopus 로고
    • Integrated circuits: Memory grows up
    • 10.1038/nnano.2010.36
    • A. Pirovano, Integrated circuits: Memory grows up., Nat. Nanotechnol. 5, 177 (2010). 10.1038/nnano.2010.36
    • (2010) Nat. Nanotechnol. , vol.5 , pp. 177
    • Pirovano, A.1
  • 17
    • 0016081559 scopus 로고
    • 10.1063/1.1663719
    • D. V. Lang, J. Appl. Phys. 45, 3023 (1974). 10.1063/1.1663719
    • (1974) J. Appl. Phys. , vol.45 , pp. 3023
    • Lang, D.V.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.