Heterogeneous SRAM cell sizing for low-power H.264 applications

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 59, Issue 10, 2012, Pages 2275-2284

  Kwon, Jinmo ^a   Chang, Ik Joon ^b   Lee, Insoo ^a   Park, Heemin ^c   Park, Jongsun ^a  

^a Korea University   (South Korea)

^b Kyung Hee University   (South Korea)

^c Yonsei University   (South Korea)

Author keywords

H.264 systems; low power static random access memory (SRAM); SRAM bit cell

Indexed keywords

CELLS; CYTOLOGY; DYNAMIC PROGRAMMING; OUTAGES;

BRUTE FORCE SEARCH; FAILURE PROBABILITY; H.264 SYSTEMS; LOW VOLTAGE OPERATION; LOW-POWER STATIC RANDOM-ACCESS MEMORY (SRAM); SRAM BIT CELL; STATIC RANDOM ACCESS MEMORY; TECHNOLOGY SCALING;

STATIC RANDOM ACCESS STORAGE;

EID: 84867333478     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2012.2185335     Document Type: Article

References (25)

1. C. P. Lin et al., "A 5 mW MPEG4 SP encoder with 2D bandwidthsharing motion estimation for mobile applications," in Proc. ISSCC Dig. Tech. Papers, Feb. 2006, pp. 1626-1635.
2. A. P. Chandrakasan, S. Sheng, and R.W. Brodersen, "Low-power digital CMOS design," IEEE J. Solid State Circuits, vol. 6, no. 5, pp. 473-484, Apr. 1992.
3. I. J. Chang et al., "Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling," IET Circuits, Devices, Syst., vol. 4, no. 6, pp. 469-478, Nov. 2010.
4. L. Chang et al., "A 5.3 GHz 8T-SRAM with operation down to 0.41 V in 65 nm CMOS," in Symp. VLSI Circuits Dig., Jun. 2007, pp. 252-253.
5. I. J. Chang et al., "A 32 kb 10T sub-threshold SRAM array with bitinterleaving and differential read scheme in 90 nm CMOS," IEEE J. Solid State Circuits, vol. 44, no. 2, pp. 650-658, Feb. 2009.
6. A.-T. Do et al., "An 8T differential SRAMwith improved noisemargin for bit-interleaving in 65 nmCMOS," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 6, pp. 1252-1263, Jun. 2011.
7. I. Chang, D. Mohapatra, and K. Roy, "A priority-based 6T/8T hybrid SRAM architecture for aggressive voltage scaling in video applications," IEEE Trans. Circuits Syst. Video Technol., vol. 21, no. 2, pp. 101-112, Feb. 2011.
8. K. Osada et al., "16.7 fA/cell tunnel-leakage-suppressed 16Mb SRAM for handling cosmic-ray-induced multi-errors," in ISSCC Dig. Tech. Papers, Feb. 2003, pp. 302-303.
9. A. K. Agarwal and S. Nassif, "The impact of random device variation on SRAM cell stability in sub-90-nm CMOS technologies," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 1, pp. 86-97, Jan. 2008.
10. A. Bhavnagarwala, X. Tang, and J. D. Meindl, "The impact of intrinsic device fluctuations onCMOS SRAM cell stability," IEEE J. Solid State Circuits, vol. 36, no. 4, pp. 658-665, Apr. 2001.
11. Y. Taur and T. H. Ning, Fundametals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 2002.
12. "H.264: Advanced Video coding for generic audiovisual services," Telecommunication Standardization Sector (ITU-T) [Online]. Available: http://www.itu.int/rec/T-REC-H.264-201003-I/en
13. E. Seevinck, F. J. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," IEEE J. Solid State Circuits, vol. 22, no. 5, pp. 748-754, Oct. 1987.
14. K. Takeda et al., "Redefinition of write-margin for next generation SRAM and write-margin monitoring circuit," in ISSCC Dig. Tech. Papers, Feb. 2006, pp. 630-631.
15. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 24, no. 12, pp. 1859-1880, Dec. 2005.
16. A. J. Bhavnagarwala, X. Tang, and J. D. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," IEEE J. Solid State Circuits, vol. 36, no. 4, pp. 658-665, Apr. 2001.
17. X. Tang, V. De, and J. D. Meindl, "Intrinsic MOSFET parameter fluctuations due to random dopant placement," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 5, no. 4, pp. 369-376, Dec. 1997.
18. V. Gupta and M. Anis, "Statistical design of the 6T SRAM bit cell," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 1, pp. 93-104, Jan. 2010.
19. S. Chien et al., "Hardware architecture design of video compression for multimedia communication systems," IEEE Commun. Mag., vol. 43, no. 8, pp. 122-131, Aug. 2005.
20. "H.264/AVC Reference Software JM 16.0," Joint Video Team (JVT) [Online]. Available: http://iphome.hhi.de/suehring/tml
21. T. Cormen et al., "Dynamic programming," in Introduction to Algorithms, 3rd ed. Cambridge, MA: MIT Press, 2009, pp. 323-369.
22. Video Test Sequence Database, [Online]. Available: ftp.tnt.uni-hannover. de/pub/svc/testsequences/
23. V. Bhaskaran and K. Konstantinides, Image and Video Compression Standards, 2nd ed. Norwell, MA: Kluwer, 1997.
24. Nanoscale Integration and Modeling (NIMO) Group, Predictive Technology Model (PTM) Website [Online]. Available: http://ptm.asu.edu
25. S.-T. Zhou, S. Katariya, H. Ghasemi, S. Draper, and N. Kim, "Total area optimization for ultra-low voltage SRAM with sizing, redundancy, and error correction codes," in Proc. IEEE Int. Conf. Comput. Design, Oct. 2010, pp. 112-117.