Redefinition of write margin for next-generation SRAM and write-margin monitoring circuit

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Takeda, Koichi ^a   Ikeda, Hidetoshi ^a   Hagihara, Yasuhiko ^a   Nomura, Masahiro ^a   Kobatake, Hiroyuki ^b  

^a NEC CORPORATION   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BICMOS TECHNOLOGY; NETWORKS (CIRCUITS);

SRAM POWER SUPPLY CIRCUIT; WRITE-MARGIN MONITORING CIRCUIT;

STATIC RANDOM ACCESS STORAGE;

EID: 39749158643     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. K. Takeda, et al., "A Read-Static-Noise-Margin-Free SRAM Cell for Low-VDD and High-Speed Applications," ISSCC Dig. Tech. Papers, pp. 478-479, Feb., 2005.
2. L. Chang, et al., "Stable SRAM Cell Design for the 32 nm Node and Beyond," Symp. VLSI Tech., pp. 128-129, June, 2005.
3. K. Zhang, et al., "3-GHz 70Mb SRAM in 65nm CMOS Technology with Integrated Column-Based Dynamic Power Supply," ISSCC Dig. Tech. Papers, pp. 474-475, Feb., 2005.
4. M. Yamaoka, et al., "Low-Power Embedded SRAM Modules with Expanded Margins for Writing," ISSCC Dig. Tech. Papers, pp. 480-481, Feb., 2005.
5. W. J. Dally and J. W. Poulton, "Digital Systems Engineering," Cambridge University Press, 1998.