Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling

IET Circuits, Devices and Systems

Volumn 4, Issue 6, 2010, Pages 469-478

  Chang, I J ^a   Park, J ^b   Kang, K ^c   Roy, K ^a  

^a PURDUE UNIVERSITY   (United States)

^b Korea University   (South Korea)

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCURATE ESTIMATION; COMPUTATIONAL SPEED; CRITICAL POINTS; ESTIMATION METHODS; FAILURE PROBABILITY; MONTE CARLO SIMULATION; NANO SCALE; OVERALL DESIGN; PARAMETRIC VARIATION; SIMULATION RESULT; SIMULATION-BASED; SRAM DESIGN; STATIC RANDOM ACCESS MEMORY; TECHNOLOGY SCALING;

ESTIMATION; LOGIC DESIGN; PROBABILITY; RAILROAD PLANT AND STRUCTURES; SAMPLING;

STATIC RANDOM ACCESS STORAGE;

EID: 78149374043     PISSN: 1751858X     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cds.2010.0137     Document Type: Article

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