An analytical approach for memristive nanoarchitectures

IEEE Transactions on Nanotechnology

Volumn 11, Issue 2, 2012, Pages 374-385

  Kavehei, Omid ^a   Al Sarawi, Said ^a   Cho, Kyoung Rok ^b   Eshraghian, Kamran ^b   Abbott, Derek ^a  

^a UNIVERSITY OF ADELAIDE   (Australia)

^b Chungbuk National University   (South Korea)

Author keywords

Complementary resistive switch; memistive device; memory; memristor; nanoarchitectures; resistive RAM

Indexed keywords

ANALYTICAL APPROACH; ARRAY SIZES; CONVENTIONAL MEMORIES; DESIGN METHODOLOGY; EMERGING TECHNOLOGIES; HIGH RESISTANCE; IV CHARACTERISTICS; MEMISTIVE DEVICE; MEMORY ARRAY; MEMRISTOR; MODELING PRINCIPLES; NANOARCHITECTURES; NANOFEATURES; NOVEL MATERIALS; PHYSICAL LIMITS; RESISTIVE MEMORIES; RESISTIVE RAMS; STORAGE MECHANISM;

DATA STORAGE EQUIPMENT; DESIGN; MEMRISTORS; PASSIVE FILTERS; RESISTORS;

RANDOM ACCESS STORAGE;

EID: 84858397700     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2011.2174802     Document Type: Article

References (47)

1. International Technology Roadmap for Semiconductors, Emerging Research Devices, 2009. [Online]. Available: http://public.itrs.net
2. A. Flocke and T. G. Noll, "Fundamental analysis of resistive nanocrossbars for the use in hybrid Nano/CMOS-memory," in Proc. 33rd Eur. Solid State Circuits Conf., ESSCIRC, 2007, Munich, Germany, pp. 328-331.
3. L. O. Chua, "Memristor-The missing circuit element," IEEE Trans. Circuit Theory, vol. 18, no. 5, pp. 507-519, Sep. 1971.
4. L. O. Chua and S. M. Kang, "Memristive devices and systems," Proc. IEEE, vol. 64, no. 2, pp. 209-223, Feb. 1976.
5. L. Chua, "Resistance switching memories are memristors," Appl. Phys. A: Mater. Sci. Process., vol. 102, pp. 765-783, 2011.
6. D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, "The missing memristor found," Nature, vol. 453, pp. 80-83, 2008.
7. Y. Pershin and M. Di Ventra, "Memory effects in complex materials and nanoscale systems," Adv. Phys., vol. 60, no. 2, pp. 145-227, 2011.
8. O.Kavehei, S. Al-Sarawi, K. R. Cho, N. Iannella, S. J. Kim, K. Eshraghian, and D. Abbott, "Memristor-based synaptic networks and logical operations using in-situ computing," in Proc. Int. Conf. Series Intell. Sens., Sens. Netw. Inf. Process., ISSNIP, Adelaide, Australia, Dec. 6-9, 2011.
9. U. Ruhrmair, C. Jaeger, M. Bator, M. Stutzmann, P. Lugli, and G. Csaba, "Applications of high-capacity crossbar memories in cryptography," IEEE Trans. Nanotechnol., vol. 10, no. 3, pp. 489-498, May 2011.
10. G. Csaba and P. Lugli, "Read-out design rules for molecular crossbar architectures," IEEE Trans. Nanotechnol., vol. 8, no. 3, pp. 369-374, May 2009.
11. A. Bushmaker, C. Chang, V. Deshpande, M. Amer, M. Bockrath, and S. Cronin, "Memristive behavior observed in defected single-walled carbon nanotubes," IEEE Trans. Nanotechnol., vol. 10, no. 3, pp. 582-586, May 2011.
12. Y. Xia, Z. Chu, W. Hung, L. Wang, and X. Song, "An integrated optimization approach for nano-hybrid circuit cell mapping," IEEE Trans. Nanotechnol., vol. 10, no. 6, pp. 1275-1284, 2011.
13. Z. Yang, C. Ko, and S. Ramanathan, "Oxide electronics utilizing ultrafast metal-insulator transitions," Annu. Rev. Mater. Res., vol. 41, pp. 337-367, 2011.
14. E. Linn, R. Rosezin, C. Kügeler, and R.Waser, "Complementary resistive switches for passive nanocrossbar memories," Nature Mater., vol. 9, no. 5, pp. 403-406, 2010.
15. S. Yu, J. Liang, Y. Wu, and H. Wong, "Read/write schemes analysis for novel complementary resistive switches in passive crossbar memory arrays," Nanotechnology, vol. 21, art. no. 465202, 2010.
16. V. Zhirnov, R. Cavin, S. Menzel, E. Linn, S. Schmelzer, D. Bräuhaus, C. Schindler, and R.Waser, "Memory devices: Energy-space-time tradeoffs," Proc. IEEE, vol. 98, no. 12, pp. 2185-2200, Dec. 2010.
17. D. B. Strukov, J. L. Borghetti, andR. S.Williams, "Coupled ionic and electronic transport model of thin-film semiconductor memristive behavior," Small, vol. 5, no. 9, pp. 1058-1063, 2009.
18. D. B. Strukov and R. S.Williams, "Exponential ionic drift: Fast switching and low volatility of thin-film memristors," Appl. Phys. A: Mater. Sci. Process., vol. 94, no. 3, pp. 515-519, 2009.
19. M. D. Pickett, D. B. Strukov, J. L. Borghetti, J. J. Yang, G. S. Snider, D. R. Stewart, and R. S. Williams, "Switching dynamics in titanium dioxide memristive devices," J. Appl. Phys., vol. 106, no. 7, pp. 074508-1-074508- 6, 2009.
20. S. Shin, K. Kim, and S. M. Kang, "Memristor applications for programmable analog ICs," IEEE Trans. Nanotechnol., vol. 10, no. 2, pp. 266-274, Mar. 2011.
21. D. Batas and H. Fiedler, "A memristor spice implementation and a new approach for magnetic flux controlled memristor modeling," IEEE Trans. Nanotechnol., vol. 10, no. 2, pp. 250-255, Mar. 2011.
22. 2/ITO memristor," Presented at 54th IEEE Int. Midwest Symp. Circuits Syst., MWS CAS, Aug. 7-10, pp. 1-4.
23. W. Yi, F. Perner, M. S. Qureshi, H. Abdalla, M. D. Pickett, J. J. Yang, M. X. M. Zhang, G. Medeiros-Ribeiro, and R. S. Williams, "Feedback write scheme for memristive switching devices," Appl. Phys. A: Mater. Sci. Process., vol. 102, pp. 973-982, 2011.
24. N. Mott and R. Gurney, Electronic Processes in Ionic Crystals. New York: Dover, 1964.
25. A. Heuer, S. Murugavel, and B. Roling, "Nonlinear ionic conductivity of thin solid electrolyte samples: Comparison between theory and experiment," Phys. Rev. B, vol. 72, no. 17, pp. 174304-1-174304-7, 2005.
26. J. P. Strachan, D. B. Strukov, J. Borghetti, J. J. Yang, G. Medeiros-Ribeiro, andR. S.Williams, "The switching location of a bipolar memristor: Chemical, thermal and structural mapping," Nanotechnology, vol. 22, no. 25, p. 254015, 2011.
27. I. Valov, R. Waser, J. R. Jameson, and M. N. Kozicki, "Electrochemical metallization memories-fundamentals, applications, prospects," Nanotechnology, vol. 22, no. 25, p. 254003, 2011.
28. K. M. Kim, D. S. Jeong, and C. S. Hwang, "Nanofilamentary resistive switching in binary oxide system: A review on the present status and outlook," Nanotechnology, vol. 22, no. 25, p. 254002, 2011.
29. D. Ielmini, F. Nardi, and C. Cagli, "Physical models of size-dependent nanofilament formation and rupture inNiO resistive switchingmemories," Nanotechnology, vol. 22, no. 25, p. 254022, 2011.
30. H. Akinaga and H. Shima, "Resistive random access memory (ReRAM) based on metal oxides," Proc. IEEE, vol. 98, no. 12, pp. 2237-2251, Dec. 2010.
31. G. Burr, M. Breitwisch, M. Franceschini, D. Garetto, K. Gopalakrishnan, B. Jackson, B. Kurdi, C. Lam, L. Lastras, A. Padilla, B. Rajendran, S. Raoux, and R. S. Shenoy, "Phase change memory technology," J. Vacuum Sci. Technol. B: Microelectron. Nanometer Struct., vol. 28, no. 2, pp. 223-262, 2010.
32. J. J. Yang, M. D. Pickett, X. Li, A. A. Ohlberg Douglas, D. R. Stewart, and R. S.Williams, "Memristive switching mechanism for metal-oxide-metal nanodevices," Nature Nanotechnol., vol. 3, pp. 429-433, 2008.
33. I. Inoue, M. Rozenberg, S. Yasuda, M. Sanchez, M. Yamazaki, T. Manago, H. Akinaga, H. Takagi, H. Akoh, and Y. Tokura, "Strong electron correlation effects in non-volatile electronic memory devices," in Proc. Non-Volatile Memory Technol. Symp., Dallas, TX, 2005, pp. 131- 136.
34. 2memristive devices electroformed at low current," Nanotechnology, vol. 22, no. 25, p. 254007, 2011.
35. Q. Xia, M. D. Pickett, J. J. Yang, M.-X. Zhang, J. Borghetti, X. Li, W.Wu, G.Medeiros-Ribeiro, and R. S.Williams, "Impact of geometry on the performance of memristive nanodevices," Nanotechnology, vol. 22, no. 25, p. 254026, 2011.
36. U. Russo,D. Ielmini, C. Cagli, A. Lacaita, S. Spiga, C.Wiemer,M. Perego, and M. Fanciulli, "Conductive-filament switching analysis and selfaccelerated thermal dissolution model for reset in NiO-based RRAM," in Proc. IEEE Int. Electron Devices Meet. (IEDM), Washington, DC, 2007, pp. 775-778.
37. U. Russo, D. Ielmini, C. Cagli, and A. Lacaita, "Filament conduction and reset mechanism in NiO-based resistive-switching memory (RRAM) devices," IEEE Trans. Electron Devices, vol. 56, no. 2, pp. 186-192, Feb. 2009.
38. R. Rosezin, E. Linn, C. Kügeler, R. Bruchhaus, and R. Waser, "Crossbar logic using bipolar and complementary resistive switches," IEEE Electron Device Lett., vol. 32, no. 6, pp. 710-712, Jun. 2011.
39. D. Strukov and R. Williams, "Four-dimensional address topology for circuits with stacked multilayer crossbar arrays," Proc. Nat. Acad. Sci., vol. 106, no. 48, pp. 20155-20158, 2009.
40. C. J. Amsinck, N. H. D. Spigna, D. P. Nackashi, and P. D. Franzon, "Scaling constraints in nanoelectronic random-access memories," Nanotechnology, vol. 16, no. 10, pp. 2251-2260, 2005.
41. 2as a resistive layer," in Proc. 8th IEEE Conf. Nanotechnol. (NANO), Arlington, TX, 2008, pp. 319-322.
42. 2-based metal-insulator-metal selection device for bipolar resistive random access memory cross-point application," J. Appl. Phys., vol. 109, no. 3, pp. 033712-1-033712-4, 2011.
43. J. Liang and H. Wong, "Cross-point memory array without cell selectorsdevice characteristics and data storage pattern dependencies," IEEE Trans. Electron Devices, vol. 57, no. 10, pp. 2531-2538, Oct. 2010.
44. S. Tappertzhofen, E. Linn, L. Nielen, R. Rosezin, F. Lentz, R. Bruchhaus, I. Valov, U. Böttger, and R.Waser, "Capacity based nondestructive readout for complementary resistive switches," Nanotechnology, vol. 22, p. 395203, 2011.
45. G. Medeiros-Ribeiro, F. Perner, R. Carter, H. Abdalla, M. D. Pickett, and R. S. Williams, "Lognormal switching times for titanium dioxide bipolar memristors: origin and resolution," Nanotechnology, vol. 22, p. 095702, 2011.
46. 2thin-film and spintronic memristors," in Proc. 16th Asia South Pacific Design Autom. Conf. (ASPDAC), Yokohama, Japan, 2011, pp. 25-30.
47. C. Xu,X.Dong, N. Jouppi, andY. Xie, "Design implications of memristorbased RRAM cross-point structures," in Proc. Design, Autom. Test Eur. Conf. Exhib. (DATE), Grenoble, France, 2011, pp. 1-6.