PARDIS: A programmable memory controller for the DDRx interfacing standards

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2012, Pages 13-24

  Bojnordi, Mahdi Nazm ^a   Ipek, Engin ^a  

^a UNIVERSITY OF ROCHESTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADVERSE EFFECT; APPLICATION-SPECIFIC OPTIMIZATIONS; CONTROL TASK; HARDWARE IMPLEMENTATIONS; HIGH-SPEED; INSTRUCTION SET ARCHITECTURE; MEMORY CONTROLLER; NAND FLASH; PERFORMANCE REQUIREMENTS; POWER MANAGEMENT ALGORITHMS; POWER MANAGEMENTS; PROGRAMMABILITY; PROGRAMMABLE MEMORY; RESOURCE CONSTRAINT;

COMPUTER ARCHITECTURE; DYNAMIC RANDOM ACCESS STORAGE; ENERGY MANAGEMENT; HARDWARE; MAPPING; SCHEDULING;

CONTROLLERS;

EID: 84864855111     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2012.6237002     Document Type: Conference Paper

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