A memory system design framework: Creating smart memories

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2009, Pages 406-417

  Firoozshahian, Amin ^a   Solomatnikov, Alex ^a   Shacham, Ofer ^b   Asgar, Zain ^b   Richardson, Stephen ^b   Kozyrakis, Christos ^b   Horowitz, Mark ^a  

^a Hicamp Systems Inc   (United States)

^b STANFORD UNIVERSITY   (United States)

Author keywords

Cache coherence; Memory access protocol; Memory systems; Multi core processors; Protocol controller; Reconfigurable architecture; Stream programming; Transactional memory

Indexed keywords

CACHE COHERENCE; MEMORY ACCESS; MEMORY SYSTEMS; MULTI-CORE PROCESSOR; PROTOCOL CONTROLLER; RECONFIGURABLE ARCHITECTURE; STREAM PROGRAMMING; TRANSACTIONAL MEMORY;

COMPUTER ARCHITECTURE; COMPUTERS; CONCURRENCY CONTROL; CONTROLLERS; HYDRAULICS; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; NETWORK ARCHITECTURE; PROGRAM PROCESSORS; STORAGE ALLOCATION (COMPUTER);

CACHE MEMORY;

EID: 70450257974     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1555754.1555805     Document Type: Conference Paper

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