A fully-programmable memory management system optimizing queue handling at multi gigabit rates

Proceedings - Design Automation Conference

Volumn , Issue , 2003, Pages 54-59

  Kornaros, G ^a   Papaefstathiou, I ^a   Nikologiannis, A ^a   Zervos, N ^a  

^a Ellemedia Technologies   (Greece)

Author keywords

Memory management; Network Processor

Indexed keywords

BANDWIDTH; COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING; EMBEDDED SYSTEMS; QUALITY OF SERVICE;

MEMORY MANAGEMENT SYSTEMS;

DATA STORAGE EQUIPMENT;

EID: 0041589403     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775848.775849     Document Type: Conference Paper

References (6)

1. B. Suter, T.V. Lakshman, D. Stiliadis, A.K. Choudhury: "Buffer Management Schemes for Supporting TCP in Gigabit Routers with Per-Flow Queueing", IEEE Journal in Selected Areas in Communications, August 1999.
2. P. Andersson, C. Svensson (Lund Univ. of Sweden): "A VLSI Architecture for an 80 Gb/s ATM Switch Core", IEEE Innovative Systems in Silicon Conference, October 1996.
3. A. Nikologiannis, M. Katevenis, "Efficient Per-Flow Queueing in DRAM at OC-192 Line Rate using Out-of-Order Execution Techniques", Proceedings of ICC2001, Helsinki, Finland, June 2001.
4. D. Whelihan and H. Schmit, "Memory optimization in single chip network switch fabric" Proceedings of the 39th conference on Design automation, New Orleans, Louisiana, USA, June 2002.
5. Ch. Ykman at all: "System-level performance optimization of the data queueing memory management in high-speed network processors", Proceedings of the 39th Conference on Design automation, New Orleans, Louisiana, USA, June 2002.
6. K.Vlachos, T.Orphanoudakis, N.Nikolaou, G.Kornaros, K.Pramataris, S.Perissakis, J-A.Sanchez, and G. Konstantoulakis. "Processing and scheduling components in an innovative network processor architecture.", Proceedings of the 16th VLSI Conference 2003, New Delhi, India, January 2003.