FabScalar: Composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2011, Pages 11-22

  Choudhary, Niket K ^a   Wadhavkar, Salil V ^a   Shah, Tanmay A ^a   Mayukh, Hiran ^a   Gandhi, Jayneel ^a   Dwiel, Brandon H ^a   Navada, Sandeep ^a   Najaf Abadi, Hashem H ^a   Rotenberg, Eric ^a  

^a North Carolina State University   (United States)

Author keywords

Custom processors; Heterogeneous (asymmetric) multi core; Instruction level parallelism (ILP); Superscalar processors

Indexed keywords

ACHILLES' HEEL; CANONICAL FORM; CUSTOM PROCESSORS; CYCLE TIME; GENERATION TOOLS; HETEROGENEOUS MULTICORE; INSTRUCTION-LEVEL PARALLELISM; MANY CORE; MULTI CORE; PIPELINE DEPTH; PROGRAM PHASIS; REGISTER TRANSFER LEVEL; RTL DESIGNS; SUPERSCALAR; SUPERSCALAR PROCESSOR; TOOLSETS;

COMPUTER ARCHITECTURE; DESIGN; MICROPROCESSOR CHIPS; MULTICORE PROGRAMMING; PARALLEL PROCESSING SYSTEMS; PIPELINES;

PIPELINE PROCESSING SYSTEMS; MULTICORE PROGRAMMING;

EID: 80052542497     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2000064.2000067     Document Type: Conference Paper

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