-
1
-
-
0030382365
-
Shared Memory Consistency Models: A Tutorial
-
Dec.
-
S.V. Adve and K. Gharachorloo, "Shared Memory Consistency Models: A Tutorial," Computer, vol. 29, no. 12, pp. 66-76, Dec. 1996.
-
(1996)
Computer
, vol.29
, Issue.12
, pp. 66-76
-
-
Adve, S.V.1
Gharachorloo, K.2
-
2
-
-
84904307796
-
The CacheMire Test Bench - A Flexible and Effective Approach for Simulation of Multiprocessors
-
M. Brorsson, F. Dahlgren, H. Nilsson, and P. Stenstrom, "The CacheMire Test Bench - A Flexible and Effective Approach for Simulation of Multiprocessors," Proc. 26th Ann. Simulation Symp., 1993.
-
(1993)
Proc. 26th Ann. Simulation Symp.
-
-
Brorsson, M.1
Dahlgren, F.2
Nilsson, H.3
Stenstrom, P.4
-
3
-
-
0018152817
-
A New Solution to Coherence Problems in Multicache Systems
-
Dec.
-
L.M. Censier and P. Feautrier, "A New Solution to Coherence Problems in Multicache Systems," IEEE Trans. Computers, vol. 27, no. 12, pp. 1,112-1,118, Dec. 1978.
-
(1978)
IEEE Trans. Computers
, vol.27
, Issue.12
-
-
Censier, L.M.1
Feautrier, P.2
-
5
-
-
0001801746
-
Protocol Verification as a Hardware Design Aid
-
Oct.
-
D.L. Dill, A.J. Drexler, A.J. Hu, and C.H. Yang, "Protocol Verification as a Hardware Design Aid," Proc. Int'l Conf. Computer Design: VLSI in Computers and Processors, pp. 522-525, Oct. 1992.
-
(1992)
Proc. Int'l Conf. Computer Design: VLSI in Computers and Processors
, pp. 522-525
-
-
Dill, D.L.1
Drexler, A.J.2
Hu, A.J.3
Yang, C.H.4
-
6
-
-
0027940807
-
Performance Optimizations and Verification Methodology of the SGI Challenge Multiprocessor
-
Jan
-
M. Galles and E. Williams, "Performance Optimizations and Verification Methodology of the SGI Challenge Multiprocessor," Proc. Hawaii Int'l Conf. System Sciences, vol. 1, pp. 134-143, Jan 1994.
-
(1994)
Proc. Hawaii Int'l Conf. System Sciences
, vol.1
, pp. 134-143
-
-
Galles, M.1
Williams, E.2
-
8
-
-
0025429467
-
The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor
-
June
-
D. Lenoski, J. Laudon, K. Gharachorloo, A. Gupta, and J. Hennessy, "The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor," Proc. 17th Int'l Symp. Computer Architecture, pp. 148-159, June 1990.
-
(1990)
Proc. 17th Int'l Symp. Computer Architecture
, pp. 148-159
-
-
Lenoski, D.1
Laudon, J.2
Gharachorloo, K.3
Gupta, A.4
Hennessy, J.5
-
9
-
-
0030284924
-
Multiprocessor Validation of the Pentium Pro
-
Nov.
-
D.T. Marr, S. Natarajan, S. Thakkar, and R. Zucker, "Multiprocessor Validation of the Pentium Pro," Computer, vol. 29, no. 11, pp. 47-53, Nov. 1996.
-
(1996)
Computer
, vol.29
, Issue.11
, pp. 47-53
-
-
Marr, D.T.1
Natarajan, S.2
Thakkar, S.3
Zucker, R.4
-
10
-
-
33747403158
-
Formal Verification of Data Type Refinement - Theory and Practice
-
Springer-Verlag, May/ June
-
T. Nipkow, "Formal Verification of Data Type Refinement - Theory and Practice," Lecture Notes in Computer Science, vol. 430, pp. 561-591. Springer-Verlag, May/ June 1989.
-
(1989)
Lecture Notes in Computer Science
, vol.430
, pp. 561-591
-
-
Nipkow, T.1
-
11
-
-
0002789786
-
The S3.mp Scalable Shared Memory Multiprocessor
-
A. Nowatzyk, G. Aybay, M. Browne, E. Kelly, M. Parkin, B. Radke, and S. Vishin, "The S3.mp Scalable Shared Memory Multiprocessor," Proc. Int'l Conf. Parallel Processing, 1995.
-
(1995)
Proc. Int'l Conf. Parallel Processing
-
-
Nowatzyk, A.1
Aybay, G.2
Browne, M.3
Kelly, E.4
Parkin, M.5
Radke, B.6
Vishin, S.7
-
12
-
-
21844487266
-
Exploiting Parallelism in Cache Coherency Protocol Engines
-
Aug.
-
A. Nowatzyk, G. Aybay, M. Browne, E. Kelly, M. Parkin, B. Radke, and S. Vishin, "Exploiting Parallelism in Cache Coherency Protocol Engines," Proc. First Int'l EURO-PAR Conf., pp. 269-286, Aug. 1995.
-
(1995)
Proc. First Int'l EURO-PAR Conf.
, pp. 269-286
-
-
Nowatzyk, A.1
Aybay, G.2
Browne, M.3
Kelly, E.4
Parkin, M.5
Radke, B.6
Vishin, S.7
-
13
-
-
0029352644
-
A New Approach for the Verification of Cache Coherence Protocols
-
Aug.
-
F. Pong and M. Dubois, "A New Approach for the Verification of Cache Coherence Protocols," IEEE Trans. Parallel and Distributed Systems, vol. 6, no. 8, pp. 773-787, Aug. 1995.
-
(1995)
IEEE Trans. Parallel and Distributed Systems
, vol.6
, Issue.8
, pp. 773-787
-
-
Pong, F.1
Dubois, M.2
-
14
-
-
84956635709
-
Verifying Distributed Directory-based Cache Coherence Protocols: S3.mp, a Case Study
-
Aug.
-
F. Pong, A. Nowatzyk, G. Aybay, and M. Dubois, "Verifying Distributed Directory-based Cache Coherence Protocols: S3.mp, a Case Study," Proc. First Int'l EURO-PAR Conf., pp. 287-300, Aug. 1995.
-
(1995)
Proc. First Int'l EURO-PAR Conf.
, pp. 287-300
-
-
Pong, F.1
Nowatzyk, A.2
Aybay, G.3
Dubois, M.4
-
15
-
-
0031084017
-
A Survey of Techniques for Verifying Cache Coherence Protocols
-
Mar.
-
F. Pong and M. Dubois, "A Survey of Techniques for Verifying Cache Coherence Protocols," ACM Computing Surveys, vol. 29, no. 1, pp. 82-126, Mar. 1997.
-
(1997)
ACM Computing Surveys
, vol.29
, Issue.1
, pp. 82-126
-
-
Pong, F.1
Dubois, M.2
-
18
-
-
0002255264
-
SPLASH: Stanford Parallel Applications for Shared-Memory
-
Mar.
-
J.P. Singh, W.-D. Weber, and A. Gupta, "SPLASH: Stanford Parallel Applications for Shared-Memory," Computer Architecture News, vol. 20, no. 1, pp. 5-44, Mar. 1992.
-
(1992)
Computer Architecture News
, vol.20
, Issue.1
, pp. 5-44
-
-
Singh, J.P.1
Weber, W.-D.2
Gupta, A.3
-
19
-
-
0025440459
-
A Survey of Cache Coherence Schemes for Multiprocessors
-
June
-
P. Stenström, "A Survey of Cache Coherence Schemes for Multiprocessors," Computer, vol. 23, no. 6, pp. 12-24, June 1990.
-
(1990)
Computer
, vol.23
, Issue.6
, pp. 12-24
-
-
Stenström, P.1
-
21
-
-
0025470393
-
Verifying a Multiprocessor Cache Controller Using Random Test Generation
-
Aug.
-
D.D. Wood, G.A. Gibson, and R.H. Katz, "Verifying a Multiprocessor Cache Controller Using Random Test Generation," IEEE Design and Test of Computers, pp. 13-25, Aug. 1990.
-
(1990)
IEEE Design and Test of Computers
, pp. 13-25
-
-
Wood, D.D.1
Gibson, G.A.2
Katz, R.H.3
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