Simultaneous branch and warp interweaving for sustained GPU performance

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2012, Pages 49-60

  Brunie, Nicolas ^a   Collange, Sylvain ^b   Diamos, Gregory ^c  

^a UNIVERSITÉ DE LYON   (France)

^b FEDERAL UNIVERSITY OF MINAS GERAIS   (Brazil)

^c NVIDIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER GRAPHICS; LOCKS (FASTENERS); PROGRAM PROCESSORS;

CONTROL LOGIC; DIVERGENTS; EXECUTION PATHS; EXECUTION UNITS; FINE GRAINED; INSTRUCTION FETCH; MICRO ARCHITECTURES; MULTIPLE THREADS; PERFORMANCE; RE CONVERGENCES;

GRAPHICS PROCESSING UNIT;

EID: 84864834311     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2366231.2337166     Document Type: Conference Paper

References (31)

1. A. S. Al-Zawawi, V. K. R eddy, E. Rotenberg, and H. H. Akkary. Transparent control independence (TCI). SIGAR CH Comput. Archit. News, 35:448-459, June 2007.
2. S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, S.-H. Lee, and K. Skadron. Rodinia: A benchmark suite for heterogeneous computing. IEEE Workload Characterization Symposium, 0:44-54, 2009.
3. S. Collange, M. Daumas, D. Defour, and D. Parello. Barra: a parallel functional simulator for GPGPU. In IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), pages 351-360, 2010.
4. S. Collange, D. Defour, and Y. Zhang. Dynamic detection of uniform and affine vectors in GPGPU computations. In Europar 3rd Workshop on Highly Parallel Processing on a Chip (HPPC), volume LNCS 6043, pages 46-55, 2009.
5. S. Collange and A. Kouyoumdjian. Affine Vector Cache for memory bandwidth savings. Technical Report ensl- 00649200, ENS Lyon, Dec. 2011.
6. J. D. Collins, D. M. Tullsen, and H. Wang. Control flow optimization via dynamic reconvergence prediction. In IEEE/ACM International Symposium on Microarchitecture, pages 129-140. IEEE Computer Society, 2004.
7. B. W. Coon, P. C. Mills, S. F. Oberman, and M. Y. Siu. Tracking register usage during multithreaded processing using a scoreboard having separate memory regions and storing sequential register size indicators. US Patent 7434032, October 2008.
8. G. Dasika, A. Sethia, T. Mudge, and S. Mahlke. PEPSC: A power-efficient processor for scientific computing. In PACT, 2011.
9. M. Dechene, E. Forbes, and E. Rotenberg. Multithreaded instruction sharing. Technical report, North Carolina State University, 2010.
10. G. Diamos, A. Kerr, H. Wu, S. Yalamanchili, B. Ashbaugh, and S. Maiyuran. SIMD re-convergence at thread frontiers. In MICRO 44: Proceedings of the 44th annual IEEE/ACM International Symposium on Microarchitecture, December 2011.
11. R. Dolbeau and A. Seznec. CASH: Revisiting hardware sharing in single-chip parallel processor. Journal of Instruction-Level Parallelism, 6:1-16, 2004.
12. R. Espasa and M. Valero. Multithreaded vector architectures. In Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture, HPCA'97, pages 237-244, 1997.
13. P. Fortin, M. Gouicem, and S. Graillat. Towards solving the table maker dilemma on GPU. In 20th Euromicro International Conference on Parallel, Distributed and Network-Based Computing (PDP 12), 2012.
14. W. Fung and T. Aamodt. Thread block compaction for efficient SIMT control flow. In 2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA), pages 25-36, February 2011.
15. W. W. L. Fung, I. Sham, G. Yuan, and T. M. Aamodt. Dynamic warp formation: Efficient MIMD control flow on SIMD graphics hardware. ACM Trans. Archit. Code Optim., 6:7:1-7:37, July 2009.
16. M. Gebhart, D. R. Johnson, D. Tarjan, S. W. Keckler, W. J. Dally, E. Lindholm, and K. Skadron. Energyefficient mechanisms for managing thread context in throughput processors. In Proceeding of the 38th annual international symposium on Computer architecture, pages 235-246, 2011.
17. A. Glew. Coherent vector lane threading. Berkeley Par- Lab Seminar, 2009.
18. R. Krashinsky, C. Batten, M. Hampton, S. Gerding, B. Pharris, J. Casper, and K. Asanovic. The Vector- Thread architecture. IEEE MICRO, 24(6):84-90, 2004.
19. R. Kumar, N. P. Jouppi, and D. M. Tullsen. Conjoinedcore chip multiprocessing. In IEEE/ACM International Symposium on Microarchitecture, pages 195-206, 2004.
20. A. Lashgar and A. Baniasadi. Performance in GPU architectures: Potentials and distances. In 9th Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD11), in conjunction with ISCA-38, 2011.
21. V. W. Lee, C. Kim, J. Chhugani, M. Deisher, D. Kim, A. D. Nguyen, N. Satish, M. Smelyanskiy, S. Chennupaty, P. Hammarlund, R. Singhal, and P. Dubey. Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU. In ISCA '10: Proceedings of the 37th annual international symposium on Computer architecture, pages 451-460, 2010.
22. J. E. Lindholm, J. Nickolls, S. Oberman, and J. Montrym. NVIDIA Tesla: A unified graphics and computing architecture. IEEE Micro, 28(2):39-55, 2008.
23. G. Long, D. Franklin, S. Biswas, P. Ortiz, J. Oberg, D. Fan, and F. T. Chong. Minimal multi-threading: Finding and removing redundant instructions in multithreaded processors. In Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO '43, pages 337-348, 2010.
24. J. Meng, D. Tarjan, and K. Skadron. Dynamic warp subdivision for int rated branch and memory divergence tolerance. SIGARCH Comput. Archit. News, 38(3):235-246, 2010.
25. P. C. Mills, J. E. Lindholm, B. W. Coon, G. M. Tarolli, and J. M. Burgess. Scheduler in multi-threaded processor prioritizing instructions passing qualification rule. US Patent 7949855, May 2011.
26. V. Narasiman, C. J. Lee, M. Shebanow, R. Miftakhutdinov, O. Mutlu, and Y. N. Patt. Improving GPU performance via large warps and two-level warp scheduling. In MICRO 44: Proceedings of the 44th annual IEEE/ACM International Symposium on Microarchitecture, December 2011.
27. J. Nickolls and W. J. Dally. The GPU computing era. IEEE Micro, 30:56-69, March 2010.
28. NVIDIA CUDA SDK, 2010. http://www. nvidia.com/cuda/.
29. K. Pagiamtzis and A. Sheikholeslami. Contentaddressable memory (CAM) circuits and architectures: a tutorial and survey. IEEE Journal of Solid-State Circuits, 41(3):712-727, march 2006.
30. S. Rivoire, R. Schultz, T. Okuda, and C. Kozyrakis. Vector lane threading. In Proceedings of the 2006 International Conference on Parallel Processing, ICPP '06, pages 55-64, 2006.
31. D. M. Tullsen, S. J. Eggers, and H. M. Levy. Simultaneous multithreading: maximizing on-chip parallelism. SIGARCH Comput. Archit. News, 23:392-403, May 1995.