Control flow optimization via dynamic reconvergence prediction

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2004, Pages 129-140

  Collins, Jamison D ^a,b   Tullsen, Dean M ^a   Wang, Hong ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROL INSTRUCTIONS; CONTROL RECONVERGENCE POINT; DYNAMIC MULTITHREADING (DMT); PREDICT CONTROL INSTRUCTION;

ALGORITHMS; BENCHMARKING; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; IDENTIFICATION (CONTROL SYSTEMS); OPTIMIZATION;

FLOW CONTROL;

EID: 21644487687     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2004.13     Document Type: Conference Paper

References (22)

1. T. Aamodt, P. Chow, P. Hammarlund, H. Wang, and J. Shen. Hardware support for prescient instruction prefetch. In To Appear in Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Feb. 2004.
2. T. Aamodt, P. Marcuello, P. Chow, A. Gonzalez, P. Hammarlund, H. Wang, and J. Shen. A framework for modeling and optimization of prescient instruction prefetch. In SIGMETRICS, June 2003.
3. H. Akkary and M. Driscoll. A dynamic multithreading processor. In Proceedings of the 31st Annual International Symposium on Microarchitecture, 30 November-2 December 1998.
4. R. Alverson, D. Callahan, D. Cummings, B. Koblenz, A. Porterfield, and B. Smith. The tera computer system. In International Conference on Supercomputing, pages 1-6, June 1990.
5. C. Cher and T. Vijaykumar. Skipper: A microarchitecture for exploiting controlflow independence. In 34th International Symposium on Microarchitecture, Nov. 2001.
6. Y. Chou, J. Fung, and J. Shen. Reducing branch misprediction penalties via dynamic control independence detection. In International Conference on SuperComputing, June 1999.
7. A. Falcón, J. Stark, A. Ramirez, K. Lai, and M. Valero. Prophet/critic hybrid branch prediction. In 31st Annual International Symposium on Computer Architecture, May 2004.
8. A. Klauser, A. Paithankar, and D. Grunwald. Selective eager execution on the polypath architecture. In 25th Annual International Symposium on Computer Architecture, June 1998.
9. P. Marcuello and A. Gonzalez. Thread-spawning schemes for multithreaded architectures. In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture, Feb. 2002.
10. P. Marcuello, A. Gonzalez, and J. Tubella. Speculative multithreaded processors. In International Conference on SuperComputing, July 1998.
11. E. Rotenberg, Q. Jacobson, and J. Smith. A study of control independence in superscalar processors. In Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, Jan. 1999.
12. E. Rotenberg and J. Smith. Control independence in trace processors. In 32nd International Symposium on Microarchitecture, June 1999.
13. A. Roth and G. Sohi. Register integration: a simple and efficient implementation of squash reuse. In MICRO33, Dec. 2000.
14. J. Seward. Valgrind, an open-source memory debugger for x86-gnu/linux. In http://valgrind.kde.org/, 2004.
15. A. Seznec, S. Felix, V. Krishnan, and Y. Sazeides. Design tradeoffs for the alpha ev8 conditional branch predictor. In 29th Annual International Symposium on Computer Architecture, May 2002.
16. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In Tenth International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 2002. http://www.cs.ucsd.edu/users/calder/simpoint/.
17. A. Sodani and G. Sohi. Dynamic instruction reuse. In ISCA97, June 1997.
18. G. Sohi, S. Breach, and T. Vijaykumar. Multiscalar processors. In 22nd Annual International Symposium on Computer Architecture, June 1995.
19. J. G. Steffan and T. C. Mowry. The potential for using thread-level data speculation to facilitate automatic parallelization. In Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Jan. 1998.
20. D. Tullsen. Simulation and modeling of a simultaneous multithreading processor. In 22nd Annual Computer Measurement Group Conference, Dec. 1996.
21. D. Tullsen, S. Eggers, and H. Levy. Simultaneous multithreading: Maximizing on-chip parallelism. In 22nd Annual International Symposium on Computer Architecture, June 1995.
22. S. Wallace, B. Calder, and D. Tullsen. Threaded multiple path execution. In 25th Annual International Symposium on Computer Architecture, June 1998.