Parasitic-insensitive linearization methods for 60-GHz 90-nm CMOS LNAs

IEEE Transactions on Microwave Theory and Techniques

Volumn 60, Issue 8, 2012, Pages 2512-2523

  Li, Wei Tsung ^a   Tsai, Jeng Han ^b   Yang, Hong Yuan ^a   Chou, Wei Hung ^c   Gea, Shyh Buu ^d   Lu, Hsin Chia ^a,e   Huang, Tian Wei ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b NATIONAL TAIWAN NORMAL UNIVERSITY   (Taiwan)

^c HTC CORPORATION   (Taiwan)

^d MINISTRY OF ECONOMIC AFFAIRS   (Taiwan)

^e Graduate Institute of Electronics Engineering   (Taiwan)

Author keywords

60 GHz; CMOS; high linearity; low noise amplifier (LNA); monolithic microwave integrated circuit (MMIC)

Indexed keywords

60 GHZ; CASCODE; CMOS; CMOS TECHNOLOGY; COMMON SOURCE; DC POWER; HIGH LINEARITY; LINEARIZATION METHODS; MILLIMETER WAVE FREQUENCIES; POST-DISTORTION;

CMOS INTEGRATED CIRCUITS; LINEARIZATION; MONOLITHIC MICROWAVE INTEGRATED CIRCUITS;

LOW NOISE AMPLIFIERS;

EID: 84864707361     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2012.2198226     Document Type: Article

References (33)

1. Draft Stand ard for Information Technology-Telecommunications and Information Exchange Between Systems-Local and Metropolitan Area Networks-Specific Requirements, Part 11: Wireless LAN Medium Access Control 5 (MAC) and Physical Layer (PHY) Specifications. Amendment 6: Enhancements for Very High Throughput in the 60 GHz Band , IEEE Stand ard P802.11ad™/D0.1, Sep. 2010.
2. H. Shimomura, A. Matsuzawa, H. Kimura, G. Hayashi, T. Hirai, and A. Kand a, "A mesh-arrayed MOSFET (MA-MOS) for high-frequency analog applications," in VLSI Tech. Symp. Dig., Jun. 1997, pp. 73-74.
3. V. Aparin, G. Brown, and L. E. Larson, "Linearization of CMOS LNA's via optimum gate biasing," in IEEE Int. Circuits Syst. Symp., May 2004, vol. 4, pp. 748-751.
4. K. Namsoo, V. Aparin, K. Barnett, and C. Persico, "A cellular-band CDMA 0.25-m CMOS LNA linearized using active post-distortion," IEEE J. Solid-State Circuits, vol. 41, no. 7, pp. 1530-1534, Jul. 2006.
5. H. Zhang, X. Fan, and E. S. Sinencio, "A low-power, linearized, ultrawideband LNA design technique," IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 320-330, Feb. 2009.
6. T.-S. Kim and B.-S. Kim, "Linearization of differential CMOS low noise amplifier using cross-coupled post distortion canceller," in IEEE Proc. RFIC Symp., Jun. 2008, pp. 83-86.
7. V. Aparin and L. E. Larson, "Modified derivative superposition method for linearizing FET low-noise amplifiers," IEEE Trans. Microw. Theory Tech., vol. 53, no. 2, pp. 571-581, Feb. 2005.
8. S. Ganesan, E. S. Sinencio, and J. S. Martinez, "A highly linear lownoise amplifier," IEEE Trans. Microw. Theory Tech., vol. 54, no. 12, pp. 4079-4085, Dec. 2006.
9. Y.-H. Kuo, J.-H. Tsai, W.-H. Chou, and T.-W. Huang, "A 24-GHz 3.8-dB NF low-noise amplifier with built-in linearizer," in Asia-Pacific Microw. Conf., Dec. 2010, pp. 1505-1508.
10. N. Li, K. Okada, T. Suzuki, T. Hirose, and A. Matsuzawa, "A threestage 60 GHz CMOS LNA using dual noise-matching technique for 5 dB NF," in Asia-Pacific Microw. Conf., Dec. 2008, pp. 1-4.
11. A. Holberg, CMOS Analog Circuit Design, 2nd ed. Oxford, U.K.: Oxford Univ. Press, 2002.
12. T. H. Lee, H. Samavati, and H. R. Rategh, "5-GHz CMOS wireless LANs," IEEE Trans.Microw. Theory Tech., vol. 50, no. 1, pp. 268-280, Jan. 2002.
13. H. Samavati, H. R. Rategh, and T. H. Lee, "A 5-GHz CMOS wireless LAN receiver front-end," IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 765-772, May 2000.
14. M. Zargari, M. Terrovitis, S. H.-M. Jen, B. J. Kaczynski, M. L. Lee, M. P.Mack, S. S. Mehta, S. Mendis, K. Onodera,H. Samavati,W.W. Si, K. Singh, A. Tabatabaei, D. Weber, D. K. Su, and B. A. Wooley, "A single-chip dual-band tri-mode CMOS transceiver for IEEE 802. 11a/b/g wireless LAN," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2239-2249, Dec. 2004.
15. B.-J. Huang, K.-Y. Lin, and H. Wang, "Millimeter-wave low power and miniature CMOS multi-cascode low-noise amplifiers with noise reduction topology," IEEE Trans. Microw. Theory Tech., vol. 57, no. 12, pp. 3049-3059, Dec. 2009.
16. K.-J. Sun, Z.-M. Tsai, K.-Y. Lin, and H. Wang, "A 10.8-GHz CMOS low-noise amplifier using parallel-resonant inductor," in IEEE MTT-S Int. Microw. Symp. Dig., 2007, pp. 1795-1798.
17. H.-K. Chiou, K.-Z. Lee, and S.-J. Wu, "A high performance -band low noise amplifier using thin-film microstrip (TFMS) lines in 0.13 m CMOS technology," in Asia-Pacific Microw. Conf., Dec. 2010, pp. 1513-1516.
18. X. Fan, H. Zhang, and E. S. Sinencio, "A noise reduction and linearity improvement technique for a differential cascode LNA," IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 588-599, Mar. 2008.
19. J.-F. Chang and Y.-S. Lin, "0.99 mW 3-10 GHz common-gate CMOS UWB LNA using T-match input network and self-body-bias technique," Electron. Lett., vol. 47, no. 11, pp. 658-659, May 2011.
20. G. Huang, T.-S. Kim, B.-S. Kim,M. Yu, and Y. Ye, "Post linearization of CMOS LNA using double cascode FETs," in IEEE Int. Circuits Syst. Symp., Sep. 2006, pp. 4499-4502.
21. T.-S. Kim and B.-S. Kim, "Post-linearization of cascode CMOS low noise amplifier using folded pMOS IMD sinker," IEEE Microw. Wireless Compon. Lett., vol. 16, no. 4, pp. 182-184, Apr. 2006.
22. D. Wu, R. Huang, W.Wong, and Y.Wang, "A 0.4-V low noise amplifier using forward body bias technology for 5 GHz application," IEEE Microw.Wireless Compon. Lett., vol. 17, no. 7, pp. 543-545, Jul. 2007.
23. S. C. Cripps, "The intercept point deception," Microw. Bytes, vol. 8, pp. 44-50, 2007.
24. I. Haroun, J. Wight, C. Plett, and A. Fathy, "Multi-band 700 MHz/2.4 GHz/60 GHz RF front-end for radio-over-fiber base stations," in Radio Wireless Symp., Jan. 2010, pp. 629-632.
25. T. Yao, M. Q. Gordon, K. K. W. Tang, K. H. K. Yau, M.-T. Yang, P. Schvan, and S. P. Voinigescu, "Algorithmic design of CMOS LNAs and PAs for 60-GHz radio," IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1044-1057, May 2007.
26. H.-Y. Yang, Y.-S. Lin, C.-C. Chen, and S. S. Wong, "A low-power -band CMOS low-noise amplifier using current-sharing technique," in IEEE Int. Circuits Syst. Symp., May 2008, pp. 964-967.
27. I. Haroun, J. Wight, C. Plett, A. Fathy, and Y.-C. Hsu, "A -band 90-nm CMOS low-noise amplifier with modified CPW transmission lines for UWB systems," in Radio Wireless Symp., Jan. 2010, pp. 368-371.
28. E. Cohen, S. Ravid, and D. Ritter, "An ultra low power LNA with 15 dB gain and 4.4 dB NF in 90 nm CMOS process for 60 GHz phase array radio," in IEEE Proc. RFIC Symp., Jun. 2008, pp. 61-64.
29. C.-C. Huang, H.-C. Kuo, T.-H. Huang, and H.-R. Chuang, "Low-power, high-gain -band CMOS low noise amplifier for microwave radiometer applications," IEEE Microw. Wireless Compon. Lett., vol. 21, no. 2, pp. 104-106, Feb. 2011.
30. A. Amer, E. Hegazi, and H. Ragai, "A low-power wideband CMOS LNA for WiMax," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 1, pp. 4-8, Jan. 2007.
31. L. F. Tiemeijer, R. M. T. Pijper, and E. van der Heijden, "Complete on-wafer noise-figure characterization of 60-GHz differential amplifiers," IEEE Trans. Microw. Theory Tech., vol. 58, no. 6, pp. 1599-1608, Jun. 2010.
32. H.-C. Yeh, Z.-Y. Liao, and H. Wang, "Analysis and design of millimeter-wave low-power CMOS LNA with transformer-multicascode topology," IEEE Trans. Microw. Theory Tech., vol. 59, no. 12, pp. 3441-3454, Dec. 2011.
33. P. Sakian, E. Janssen, A. H. M. van Roermund, and R. Mahmoudi, "Analysis and design of a 60 GHz wideband voltage-voltage transformer feedback LNA," IEEE Trans. Microw. Theory Tech., vol. 60, no. 3, pp. 702-713, Mar. 2012.