Linearization of CMOS LNA'S VIA optimum gate biasing

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2004, Pages

  Aparin, Vladimir ^a   Brown, Gary ^a   Larson, Lawrence E ^b  

^a QUALCOMM INC   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACOUSTIC IMPEDANCE; AMPLIFICATION; CODE DIVISION MULTIPLE ACCESS; ELECTRIC CURRENTS; FEEDBACK CONTROL; LINEARIZATION; MATHEMATICAL MODELS; OPTIMAL CONTROL SYSTEMS; OPTIMIZATION; SENSITIVITY ANALYSIS; TRANSCONDUCTANCE; VOLTAGE CONTROL;

BIAS CIRCUITS; CELLULAR BANDS; DESENSITIZATION METHOD; DRAIN SOURCE VOLTAGES;

CMOS INTEGRATED CIRCUITS;

EID: 4344655384     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. V. Aparin and L. E. Larson, "Linearization of monolithic LNAs using low-frequency low-impedance input termination," Europ. Solid-State Circ. Conf., pp. 137-140, Sept. 2003.
2. Y. Ding and R. Harjani, "A +18dBm IIP3 LNA in 0.35um CMOS," IEEE ISSCC, pp. 162-163, 2001.
3. G. Qu and A. E. Parker "Analysis of intermodulation nulling in HEMTs," Conf. on Optoelectr. & Microelectr. Mat. & Dev., pp. 227-230, Dec. 1996.
4. M. J. M. Pelgrom, H. P. Tuinhout, and M. Vertregt, "Transistor matching in analog CMOS applications," IEDM Dig., pp. 915-918, Dec. 1998.