A single-chip dual-band Tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 12, 2004, Pages 2239-2249

  Zargari, Masoud ^a   Terrovitis, Manolis ^a   Jen, Steve Hung Min ^a   Kaczynski, Brian J ^a   Lee, Meelan ^a   Mack, Michael P ^a   Mehta, Srenik S ^a   Mendis, Sunetra ^a   Onodera, Keith ^a   Samavati, Hirad ^a   Si, William W ^a   Singh, Kalwant ^a   Tabatabaei, Ali ^b   Weber, David ^a   Su, David K ^a   Wooley, Bruce A ^c  

^a Atheros Communications   (United States)

^b IRF Semiconductor USA   (United States)

^c Stanford University   (United States)

Author keywords

Frequency synthesizer; IEEE 802.11a; IEEE 802.11b; IEEE 802.11g; Low noise amplifier (LNA); Orthogonal frequency division multiplexing (OFDM); Power amplifier; RF transceiver; Wireless LAN (WLAN)

Indexed keywords

CMOS INTEGRATED CIRCUITS; ERROR ANALYSIS; FREQUENCY SYNTHESIZERS; LOCAL AREA NETWORKS; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING; POWER AMPLIFIERS; STANDARDS; VECTORS; WIRELESS TELECOMMUNICATION SYSTEMS;

IEEE 802.11A; IEEE 802.11B; IEEE 802.11G; LOW-NOISE AMPLIFIERS (LNA); RF TRANSCEIVERS; WIRELESS LOCAL AREA NETWORK (WLAN);

TRANSCEIVERS;

EID: 10344267525     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.836349     Document Type: Conference Paper

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