Carrier-mobility enhancement via strain engineering in future thin-body MOSFETs

IEEE Electron Device Letters

Volumn 33, Issue 3, 2012, Pages 318-320

  Xu, Nuo ^a   Ho, Byron ^a   Andrieu, François ^b   Smith, Lee ^c   Nguyen, Bich Yen ^d   Weber, Olivier ^b   Poiroux, Thierry ^b   Faynot, Olivier ^b   Liu, Tsu Jae King ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b CEA LETI   (France)

^c SYNOPSYS INC   (United States)

^d Soitec   (United States)

Author keywords

Carrier mobility; FinFET; fully depleted silicon on insulator (FD SOI); high k metal gate; strain; ultra thin body and BOX

Indexed keywords

CMOSFETS; DEVICE PERFORMANCE; FINFET; FULLY DEPLETED SILICON-ON-INSULATOR; FUTURE TECHNOLOGIES; GATE STACKS; HIGH-K/METAL GATE; MEASURED DATA; MOSFETS; QUANTUM-MECHANICAL SIMULATION; STRAIN ENGINEERING; THIN BODY; ULTRA-THIN-BODY;

ELECTRON DEVICES; ELECTRONICS ENGINEERING; STRAIN;

CARRIER MOBILITY;

EID: 84863393587     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2011.2179113     Document Type: Article

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