Three-dimensional stress engineering in FinFETs for mobility/on-current enhancement and gate current reduction

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2008, Pages 18-19

  Saitoh, Masumi ^a   Kaneko, Akio ^a   Okano, Kimitoshi ^a   Kinoshita, Tomoko ^a   Inaba, Satoshi ^a   Toyoshima, Yoshiaki ^a   Uchida, Ken ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

THREE DIMENSIONAL;

AND GATES; CURRENT ENHANCEMENT; FINFETS; ON CURRENTS; STRESS ENGINEERING; SYSTEMATIC STUDY; UNIAXIAL STRESSES; VLSI TECHNOLOGIES;

TECHNOLOGY;

EID: 51949106180     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2008.4588547     Document Type: Conference Paper

References (9)

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4. S. E. Thompson et al., ED 53, 1010 (2006).
5. K.-N. Yang et al., ED 47, 2161 (2000).
6. K. Uchida et al., IEDM2006, p.711.
7. M. Saitoh et al., IEDM2007, p.1019.
8. Y. Mishima et al., JJAP 46, 943 (2007).
9. H. R. Harris et al., IEDM2007, p.57.