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Volumn , Issue , 2008, Pages 314-321

Optimization-based framework for simultaneous circuit-and-system design-space exploration: A high-speed link example

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DESIGN; INTERCONNECTION NETWORKS; OPTIMIZATION; POWER QUALITY; SPACE RESEARCH;

EID: 57849123638     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2008.4681592     Document Type: Conference Paper
Times cited : (17)

References (18)
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    • B. Casper, M. Haycock, and R. Mooney, "An accurate and efficient analysis method for multi-gb/s chip-to-chip signaling schemes," Symposium on VLSI Circuits Digest of Technical Papers, 2002., no. SN -, pp. 54-57, 2002.
    • (2002) , Issue.SN , pp. 54-57
    • Casper, B.1    Haycock, M.2    Mooney, R.3
  • 4
    • 37849188547 scopus 로고    scopus 로고
    • A study of the optimal data rate for minimum power of i/os
    • SN, 1057-7130, pp
    • H. Hatamkhani and C. Ken Yang, "A study of the optimal data rate for minimum power of i/os," IEEE Transactions on Circuits and Systems II, vol. 53, no. 11 SN - 1057-7130, pp. 1230-1234, 2006.
    • (2006) IEEE Transactions on Circuits and Systems II , vol.53 , Issue.11 , pp. 1230-1234
    • Hatamkhani, H.1    Ken Yang, C.2
  • 8
    • 0242611951 scopus 로고    scopus 로고
    • Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
    • D. Colleran, C. Portmann, A. Hassibi, C. Crusius, S. Mohan, S. Boyd, T. Lee, and M. del Mar Hershenson, "Optimization of phase-locked loop circuits via geometric programming," Proceedings of the IEEE Custom Integrated Circuits Conference, 2003., no. SN -, pp. 377-380, 2003.
    • (2003) , Issue.SN , pp. 377-380
    • Colleran, D.1    Portmann, C.2    Hassibi, A.3    Crusius, C.4    Mohan, S.5    Boyd, S.6    Lee, T.7    del Mar Hershenson, M.8
  • 12
    • 16244410115 scopus 로고    scopus 로고
    • Techniques for improving the accuracy of geometric-programming based analog circuit design optimization
    • 1092-3152, pp
    • J. Kim, J. Lee, L. Vandenberghe, and C. Yang, "Techniques for improving the accuracy of geometric-programming based analog circuit design optimization," IEEE/ACM International Conference on Computer Aided Design (ICCAD), no. SN - 1092-3152, pp. 863-870, 2004.
    • (2004) IEEE/ACM International Conference on Computer Aided Design (ICCAD) , Issue.SN , pp. 863-870
    • Kim, J.1    Lee, J.2    Vandenberghe, L.3    Yang, C.4
  • 13
    • 0035209035 scopus 로고    scopus 로고
    • Simulation-based automatic generation of signomial and posynomial performance models for analog integrated circuit sizing
    • W. Daems, G. Gielen, and W. Sansen, "Simulation-based automatic generation of signomial and posynomial performance models for analog integrated circuit sizing," IEEE/ACM International Conference on Computer Aided Design (ICCAD), no. SN -, pp. 70-74, 2001.
    • (2001) IEEE/ACM International Conference on Computer Aided Design (ICCAD) , Issue.SN , pp. 70-74
    • Daems, W.1    Gielen, G.2    Sansen, W.3
  • 14
    • 4143134378 scopus 로고    scopus 로고
    • Optimal linear precoding with theoretical and practical data rates in high-speed serial-link backplane communication
    • 5
    • V. Stojanovic, A. Amirkhany, and M. Horowitz, "Optimal linear precoding with theoretical and practical data rates in high-speed serial-link backplane communication," IEEE International Conference on Communications, vol. 5, no. SN -, pp. 2799-2806 Vol.5, 2004.
    • (2004) IEEE International Conference on Communications , vol.5 , Issue.SN , pp. 2799-2806
    • Stojanovic, V.1    Amirkhany, A.2    Horowitz, M.3
  • 17
    • 0141538244 scopus 로고    scopus 로고
    • R. Farjad-Rad, N. Hiok-Taiq, M. Edward Lee, R. Senthinathan, W. Dally, A. Nguyen, R. Rathi, J. Poulton, J. Edmondson, J. Tran, and H. Yazdanmehr, 0.622-8.0 gbps 150 mw serial io macrocell with fully flexible preemphasis and equalization, Symposium on VLSI Circuits, 2003. Digest of Technical Papers. 2003, no. SN -, pp. 63-66, 2003.
    • R. Farjad-Rad, N. Hiok-Taiq, M. Edward Lee, R. Senthinathan, W. Dally, A. Nguyen, R. Rathi, J. Poulton, J. Edmondson, J. Tran, and H. Yazdanmehr, "0.622-8.0 gbps 150 mw serial io macrocell with fully flexible preemphasis and equalization," Symposium on VLSI Circuits, 2003. Digest of Technical Papers. 2003, no. SN -, pp. 63-66, 2003.
  • 18
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    • J. Zerbe, C. Werner, V. Stojanovic, F. Chen, J. Wei, G. Tsang, D. Kim, W. Stonecypher, A. Ho, T. Thrush, R. Kollipara, M. Horowitz, and K. Donnelly, Equalization and clock recovery for a 2.5-10-gb/s 2-pam/4-pam backplane transceiver cell, IEEE Journal of Solid-State Circuits, 38, no. 12 SN - 0018-9200, pp. 2121-2130, 2003.
    • J. Zerbe, C. Werner, V. Stojanovic, F. Chen, J. Wei, G. Tsang, D. Kim, W. Stonecypher, A. Ho, T. Thrush, R. Kollipara, M. Horowitz, and K. Donnelly, "Equalization and clock recovery for a 2.5-10-gb/s 2-pam/4-pam backplane transceiver cell," IEEE Journal of Solid-State Circuits, vol. 38, no. 12 SN - 0018-9200, pp. 2121-2130, 2003.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.