Formal verification of phase-locked loops using reachability analysis and continuization

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2011, Pages 659-666

  Althoff, Matthias ^a   Yaldiz, Soner ^a   Rajhans, Akshay ^a   Li, Xin ^a   Krogh, Bruce H ^a   Pileggi, Larry ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CONTROL CIRCUIT; BEHAVIORAL MODEL; CHARGE PUMP; CHARGE PUMP PLL; CHARGE-PUMP PHASE-LOCKED LOOPS; CMOS SOI TECHNOLOGY; CONTINUOUS DYNAMICS; CONTINUOUS MODELS; DETAILED MODELS; DISCRETE TIME LINEAR SYSTEMS; FORMAL VERIFICATIONS; INITIAL STATE; LIMIT CYCLE; MONTE CARLO SIMULATION; REACHABILITY; REACHABILITY ANALYSIS; SWITCHING CONDITIONS; UNCERTAIN PARAMETERS; UNIQUE FEATURES;

ANALOG CIRCUITS; CHARGE PUMP CIRCUITS; COMPUTER AIDED ANALYSIS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; DYNAMICS; HYBRID SYSTEMS; LINEAR SYSTEMS; MONTE CARLO METHODS; PHASE LOCKED LOOPS; UNCERTAINTY ANALYSIS;

MATHEMATICAL MODELS;

EID: 84862953445     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2011.6105400     Document Type: Conference Paper

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