Advanced methods for equivalence checking of analog circuits with strong nonlinearities

Formal Methods in System Design

Volumn 36, Issue 2, 2010, Pages 131-147

  Steinhorst, Sebastian ^a   Hedrich, Lars ^a  

^a GOETHE UNIVERSITY   (Germany)

Author keywords

Analog circuits; Equivalence checking; Formal verification

Indexed keywords

CIRCUIT ELEMENTS; EIGENVALUES; EQUIVALENCE CHECKING; FALSE NEGATIVES; FLOATING NODES; FORMAL VERIFICATIONS; REACHABILITY ANALYSIS; STATE SPACE; STRONG NONLINEARITY; STRONGLY NONLINEAR; STRUCTURAL RECOGNITION;

DIGITAL CIRCUITS; DIGITAL LIBRARIES; EIGENVALUES AND EIGENFUNCTIONS;

ANALOG CIRCUITS;

EID: 77955713997     PISSN: 09259856     EISSN: None     Source Type: Journal    
DOI: 10.1007/s10703-009-0086-9     Document Type: Article

References (17)

1. Gielen GGE (2005) Cad tools for embedded analogue circuits in mixed-signal integrated systems on chip. Comput Digit Tech IEE Proc 152(3):317-332
2. Henzinger TA, Ho P-H (1995) Algorithmic analysis of nonlinear hybrid systems. In: CAV '95: International conference on computer-aided verification. LNCS, vol 939(7). Springer, Berlin, pp 225-238
3. Dang T, Donze A, Maler O (2004) Verification of analog and mixed-signal circuits using hybrid system techniques. In: FMCAD 04: Formal methods in computer-aided design
4. Al-Sammane G, Zaki MH, Tahar S (2007) A symbolic methodology for the verification of analog and mixed signal designs. In: DATE '07: Proceedings of the conference on design, automation and test in Europe, pp 249-254
5. Frehse G, Krogh BH, Rutenbar RA (2006) Verifying analog oscillator circuits using forward/backward abstraction refinement. In: DATE '06: Proceedings of the conference on design, automation and test in Europe, pp 257-262
6. Hartong W, Hedrich L, Barke E (2002) On discrete modeling and model checking for nonlinear analog systems. In: CAV '02: International conference on computer-aided verification. LNCS, vol 2404. Springer, Berlin, pp 401-413
7. Dastidar TR, Chakrabarti PP (2005) A verification system for transient response of analog circuits using model checking. In: VLSID '05: International conference on VLSI design, pp 195-200
8. Grabowski D, Olbrich M, Grimm Ch, Barke E (2008) Analog circuit simulation using range arithmetics. In: ASPDAC, pp 762-767
9. Zaki MH, Tahar S, Bois G (2006) Formal verification of analog and mixed signal designs: survey and comparison. In: IEEE north-east workshop on circuits and systems, pp 281-284
10. Hedrich L, Barke E (1995) A formal approach to nonlinear analog circuit verification. In: ICCAD '95: International conference on computer aided design, pp 123-127
11. HartongW, Klausen R, Hedrich L (2004) Formal verification for nonlinear analog systems: approaches to model and equivalence checking. In: Drechsler R. (ed) Advanced formal verification. Kluwer Academic, Boston, pp 205-245
12. Ho CW, Ruehli AE, Brennan PA (1975) The modified nodal approach to network analysis. IEEE Trans Circuits Syst 22(6):504-509
13. Hedrich L, Hartong W (2001) Approaches to formal verification of analog circuits. In: Wambacq P (ed) Low-power design techniques and CAD tools for analog and RF integrated circuits. Kluwer Academic, Boston, pp 155-191
14. März R (1991) Numerical methods for differential algebraic equations. Acta Numer 141-198
15. Van Dooren P (1979) The computation of Kronecker's canonical form of a singular pencil. J Linear Algebra Appl 27:103-140
16. Fortuna L, Nunnari G, Gallo A (1992) Model order reduction techniques with applications in electrical engineering. Springer, Berlin
17. Feldmann P, Freund RW (1995) Efficient linear circuits analysis by Pade approximation via the Lanczos process. IEEE Trans Comput-Aided Des Integr Circuits Syst 14(5):639-649