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Volumn 153, Issue 3 SPEC. ISS., 2006, Pages 37-52
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Time Constrained Verification of Analog Circuits using Model-Checking Algorithms
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Author keywords
Analog Circuits; CTL; Model Checking; Time Constraints
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Indexed keywords
CONSTRAINT THEORY;
INTEGRATED CIRCUITS;
MATHEMATICAL MODELS;
SPECIFICATIONS;
ANALOG CIRCUITS;
CTL;
MODEL CHECKING;
TIME CONSTRAINTS;
ANALOG COMPUTERS;
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EID: 33744778417
PISSN: 15710661
EISSN: None
Source Type: Journal
DOI: 10.1016/j.entcs.2006.01.026 Document Type: Article |
Times cited : (10)
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References (10)
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